2.5 分频.txt

一个VHDL电梯控制器的程序 1、 每层电梯的入口处设有上下请求开关

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIVn_5 IS
PORT ( 
         CLK  :  IN  STD_LOGIC;
        NCLK  :  BUFFER  STD_LOGIC ) ;
END DIVn_5 ;

ARCHITECTURE BEHAV OF DIVn_5  IS
SIGNAL COUNTER : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
SIGNAL SIG_CLK : STD_LOGIC ;
SIGNAL LCLK    : STD_LOGIC;
SIGNAL PCLK    : STD_LOGIC;

BEGIN
LCLK <= CLK XOR PCLK;

PROCESS(COUNTER,LCLK)
BEGIN
   IF RISING_EDGE(LCLK) THEN
       IF COUNTER = "010" THEN
          SIG_CLK <= '1';
          COUNTER<="000";
       ELSE
          SIG_CLK <= '0';
          COUNTER<=COUNTER+1;
       END IF;
   END IF;
END PROCESS;


PROCESS(SIG_CLK)
BEGIN
   IF RISING_EDGE(SIG_CLK)  THEN
       PCLK <= NOT PCLK;
   END IF;
END PROCESS;
NCLK <= SIG_CLK;
END BEHAV;