📄 max232.rpt
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# _LC1_A15 & !time0~713 & time1~713;
-- Node name is ':836' = 'time1'
-- Equation name is 'time1', location is LC4_A11, type is buried.
time1 = DFFE( _EQ025, GLOBAL( clk), VCC, VCC, VCC);
_EQ025 = _LC3_A11 & time0 & !time1
# _LC3_A11 & !time0 & time1;
-- Node name is ':953' = 'time2~713'
-- Equation name is 'time2~713', location is LC6_A15, type is buried.
time2~713 = DFFE( _EQ026, CLKK, VCC, VCC, VCC);
_EQ026 = _LC1_A15 & !time0~713 & time2~713
# _LC1_A15 & !time1~713 & time2~713
# _LC1_A15 & time0~713 & time1~713 & !time2~713;
-- Node name is ':835' = 'time2'
-- Equation name is 'time2', location is LC6_A11, type is buried.
time2 = DFFE( _EQ027, GLOBAL( clk), VCC, VCC, VCC);
_EQ027 = _LC3_A11 & !time0 & time2
# _LC3_A11 & !time1 & time2
# _LC3_A11 & time0 & time1 & !time2;
-- Node name is ':952' = 'time3~713'
-- Equation name is 'time3~713', location is LC7_A15, type is buried.
time3~713 = DFFE( _EQ028, CLKK, VCC, VCC, VCC);
_EQ028 = _LC1_A15 & !_LC2_A15 & time3~713
# _LC1_A15 & _LC2_A15 & !time3~713;
-- Node name is ':834' = 'time3'
-- Equation name is 'time3', location is LC2_A11, type is buried.
time3 = DFFE( _EQ029, GLOBAL( clk), VCC, VCC, VCC);
_EQ029 = _LC1_A11 & !time3 & !time4
# !_LC1_A11 & time3 & !time4;
-- Node name is ':951' = 'time4~713'
-- Equation name is 'time4~713', location is LC8_A15, type is buried.
time4~713 = DFFE( _EQ030, CLKK, VCC, VCC, VCC);
_EQ030 = _LC2_A15 & time3~713 & !time4~713
# !time3~713 & time4~713;
-- Node name is ':833' = 'time4'
-- Equation name is 'time4', location is LC8_A9, type is buried.
time4 = DFFE( _EQ031, GLOBAL( clk), VCC, VCC, VCC);
_EQ031 = _LC1_A11 & time3 & !time4
# !_LC1_A11 & !time3 & time4;
-- Node name is 'txd'
-- Equation name is 'txd', type is output
txd = _LC3_A9;
-- Node name is ':13' = 'TXDF'
-- Equation name is 'TXDF', location is LC1_A1, type is buried.
TXDF = DFFE( _EQ032, CLKK, WR, VCC, VCC);
_EQ032 = TXDF
# _LC1_A9 & _LC2_A9 & SCIT_V5;
-- Node name is ':4' = 'WR'
-- Equation name is 'WR', location is LC5_A23, type is buried.
WR = DFFE( _EQ033, CLKK, VCC, VCC, VCC);
_EQ033 = _LC1_A15 & WR
# !_LC1_A15 & !WR;
-- Node name is '|LPM_ADD_SUB:82|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ034);
_EQ034 = M0 & M1 & M2 & M3;
-- Node name is '|LPM_ADD_SUB:82|addcore:adder|:151' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ035);
_EQ035 = !M2 & M3
# !M0 & M3
# !M1 & M3
# M0 & M1 & M2 & !M3;
-- Node name is '|LPM_ADD_SUB:82|addcore:adder|:154' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ036);
_EQ036 = !M5 & M6
# !M4 & M6
# !_LC1_A5 & M6
# _LC1_A5 & M4 & M5 & !M6;
-- Node name is '|LPM_ADD_SUB:459|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ037);
_EQ037 = SCIT_V0 & SCIT_V1;
-- Node name is '|LPM_ADD_SUB:459|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ038);
_EQ038 = _LC1_A9 & SCIT_V2;
-- Node name is '|LPM_ADD_SUB:459|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ039);
_EQ039 = _LC1_A9 & SCIT_V2 & SCIT_V3;
-- Node name is '|LPM_ADD_SUB:855|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = LCELL( _EQ040);
_EQ040 = time0 & time1 & time2;
-- Node name is ':114'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ041);
_EQ041 = !_LC3_A12
# _LC4_A12;
-- Node name is ':119'
-- Equation name is '_LC4_A12', type is buried
_LC4_A12 = LCELL( _EQ042);
_EQ042 = _LC1_A5 & M4 & M5
# !M4 & !M5
# !_LC1_A5 & !M5
# _LC1_A5 & _LC2_A5 & M4
# !_LC1_A5 & _LC2_A5 & !M4;
-- Node name is '~121~1'
-- Equation name is '~121~1', location is LC2_A5, type is buried.
-- synthesized logic cell
_LC2_A5 = LCELL( _EQ043);
_EQ043 = M0 & M1 & M2 & M3
# !M0 & !M2 & !M3
# !M1 & !M2 & !M3;
-- Node name is ':361'
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = LCELL( _EQ044);
_EQ044 = SCIT_V5
# _LC2_A9;
-- Node name is ':363'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ045);
_EQ045 = SCIT_V2 & SCIT_V3 & SCIT_V4;
-- Node name is ':482'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ046);
_EQ046 = !_LC4_A9 & !TXDF & WR;
-- Node name is '~830~1'
-- Equation name is '~830~1', location is LC3_A8, type is buried.
-- synthesized logic cell
_LC3_A8 = LCELL( _EQ047);
_EQ047 = DIN_LATCH2 & !SCIT_V2
# DIN_LATCH3 & SCIT_V2;
-- Node name is '~830~2'
-- Equation name is '~830~2', location is LC4_A8, type is buried.
-- synthesized logic cell
_LC4_A8 = LCELL( _EQ048);
_EQ048 = _LC3_A8 & !SCIT_V4
# DIN_LATCH6 & !SCIT_V2 & SCIT_V4;
-- Node name is '~830~3'
-- Equation name is '~830~3', location is LC6_A8, type is buried.
-- synthesized logic cell
_LC6_A8 = LCELL( _EQ049);
_EQ049 = DIN_LATCH0 & !SCIT_V2 & !SCIT_V4
# DIN_LATCH1 & SCIT_V2 & !SCIT_V4;
-- Node name is '~830~4'
-- Equation name is '~830~4', location is LC8_A8, type is buried.
-- synthesized logic cell
_LC8_A8 = LCELL( _EQ050);
_EQ050 = DIN_LATCH4 & !SCIT_V2 & SCIT_V4
# DIN_LATCH5 & SCIT_V2 & SCIT_V4;
-- Node name is '~830~5'
-- Equation name is '~830~5', location is LC2_A8, type is buried.
-- synthesized logic cell
_LC2_A8 = LCELL( _EQ051);
_EQ051 = _LC4_A8 & SCIT_V3
# _LC6_A8 & !SCIT_V3
# _LC8_A8 & !SCIT_V3;
-- Node name is ':830'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ052);
_EQ052 = _LC2_A8 & SCIT_V5
# !_LC2_A9 & !SCIT_V5;
-- Node name is ':861'
-- Equation name is '_LC3_A11', type is buried
_LC3_A11 = LCELL( _EQ053);
_EQ053 = _LC1_A11 & time3
# !_LC1_A11 & !time3
# !time3 & !time4
# !_LC1_A11 & !time4;
-- Node name is ':981'
-- Equation name is '_LC1_A15', type is buried
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ054);
_EQ054 = !_LC2_A15 & time3~713 & time4~713;
-- Node name is ':988'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ055);
_EQ055 = time0~713 & time1~713 & time2~713;
Project Information c:\myproject24\max232.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,462K
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