📄 max232.rpt
字号:
- 7 - A 01 AND2 0 2 0 1 |LPM_ADD_SUB:459|addcore:adder|:71
- 2 - A 01 AND2 0 3 0 2 |LPM_ADD_SUB:459|addcore:adder|:75
- 1 - A 11 AND2 0 3 0 4 |LPM_ADD_SUB:855|addcore:adder|:67
- 5 - A 23 DFFE 0 2 0 16 WR (:4)
- 2 - A 12 DFFE 0 5 0 1 DIN_LATCH6 (:6)
- 1 - A 12 DFFE 0 4 0 1 DIN_LATCH5 (:7)
- 7 - A 08 DFFE 0 3 0 1 DIN_LATCH4 (:8)
- 8 - A 05 DFFE 0 5 0 1 DIN_LATCH3 (:9)
- 6 - A 05 DFFE 0 4 0 1 DIN_LATCH2 (:10)
- 1 - A 06 DFFE 0 3 0 1 DIN_LATCH1 (:11)
- 5 - A 08 DFFE 0 2 0 1 DIN_LATCH0 (:12)
- 1 - A 01 DFFE 0 5 0 1 TXDF (:13)
- 5 - A 09 DFFE + 0 3 0 14 CLKK (:14)
- 4 - A 15 DFFE 0 4 1 0 LED (:27)
- 7 - A 12 DFFE 0 3 0 2 M6 (:36)
- 8 - A 12 DFFE 0 4 0 4 M5 (:37)
- 5 - A 12 DFFE 0 3 0 6 M4 (:38)
- 4 - A 05 DFFE 0 3 0 4 M3 (:39)
- 7 - A 05 DFFE 0 4 0 5 M2 (:40)
- 5 - A 05 DFFE 0 3 0 7 M1 (:41)
- 1 - A 08 DFFE 0 2 0 9 M0 (:42)
- 6 - A 12 OR2 0 2 0 6 :114
- 4 - A 12 OR2 0 4 0 2 :119
- 2 - A 05 OR2 s 0 4 0 1 ~121~1
- 6 - A 01 DFFE 0 4 0 3 SCIT_V5 (:336)
- 4 - A 01 DFFE 0 4 0 5 SCIT_V4 (:337)
- 8 - A 01 DFFE 0 4 0 3 SCIT_V3 (:338)
- 3 - A 01 DFFE 0 4 0 7 SCIT_V2 (:339)
- 6 - A 09 DFFE 0 3 0 1 SCIT_V1 (:340)
- 7 - A 09 DFFE 0 2 0 2 SCIT_V0 (:341)
- 4 - A 09 OR2 0 2 0 6 :361
- 2 - A 09 AND2 0 3 0 4 :363
- 5 - A 01 AND2 0 3 0 3 :482
- 3 - A 08 OR2 s 0 3 0 1 ~830~1
- 4 - A 08 OR2 s 0 4 0 1 ~830~2
- 6 - A 08 OR2 s 0 4 0 1 ~830~3
- 8 - A 08 OR2 s 0 4 0 1 ~830~4
- 2 - A 08 OR2 s 0 4 0 1 ~830~5
- 3 - A 09 OR2 0 3 1 0 :830
- 8 - A 09 DFFE + 0 2 0 3 time4 (:833)
- 2 - A 11 DFFE + 0 2 0 3 time3 (:834)
- 6 - A 11 DFFE + 0 3 0 1 time2 (:835)
- 4 - A 11 DFFE + 0 2 0 2 time1 (:836)
- 5 - A 11 DFFE + 0 1 0 3 time0 (:837)
- 3 - A 11 OR2 0 3 0 3 :861
- 8 - A 15 DFFE 0 3 0 2 time4~713 (:951)
- 7 - A 15 DFFE 0 3 0 3 time3~713 (:952)
- 6 - A 15 DFFE 0 4 0 1 time2~713 (:953)
- 3 - A 15 DFFE 0 3 0 2 time1~713 (:954)
- 5 - A 15 DFFE 0 2 0 3 time0~713 (:955)
- 1 - A 15 AND2 ! 0 3 0 5 :981
- 2 - A 15 AND2 0 3 0 4 :988
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\myproject24\max232.rpt
max232
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 22/ 48( 45%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\myproject24\max232.rpt
max232
** CLOCK SIGNALS **
Type Fan-out Name
DFF 17 WR
DFF 15 CLKK
INPUT 6 clk
Device-Specific Information: c:\myproject24\max232.rpt
max232
** CLEAR SIGNALS **
Type Fan-out Name
DFF 17 WR
Device-Specific Information: c:\myproject24\max232.rpt
max232
** EQUATIONS **
clk : INPUT;
-- Node name is 'AD_RAM_LED'
-- Equation name is 'AD_RAM_LED', type is output
AD_RAM_LED = LED;
-- Node name is ':14' = 'CLKK'
-- Equation name is 'CLKK', location is LC5_A9, type is buried.
CLKK = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = CLKK & _LC1_A11 & time3
# CLKK & !_LC1_A11 & !time3
# CLKK & !time3 & !time4
# CLKK & !_LC1_A11 & !time4
# !CLKK & _LC1_A11 & !time3 & time4
# !CLKK & !_LC1_A11 & time3 & time4;
-- Node name is ':12' = 'DIN_LATCH0'
-- Equation name is 'DIN_LATCH0', location is LC5_A8, type is buried.
DIN_LATCH0 = DFFE(!M0, WR, VCC, VCC, VCC);
-- Node name is ':11' = 'DIN_LATCH1'
-- Equation name is 'DIN_LATCH1', location is LC1_A6, type is buried.
DIN_LATCH1 = DFFE( _EQ002, WR, VCC, VCC, VCC);
_EQ002 = M0 & !M1
# !M0 & M1;
-- Node name is ':10' = 'DIN_LATCH2'
-- Equation name is 'DIN_LATCH2', location is LC6_A5, type is buried.
DIN_LATCH2 = DFFE( _EQ003, WR, VCC, VCC, VCC);
_EQ003 = M0 & M1 & !M2
# !M0 & M2
# !M1 & M2;
-- Node name is ':9' = 'DIN_LATCH3'
-- Equation name is 'DIN_LATCH3', location is LC8_A5, type is buried.
DIN_LATCH3 = DFFE( _EQ004, WR, VCC, VCC, VCC);
_EQ004 = M0 & M1 & M2 & !M3
# !M0 & M3
# !M1 & M3
# !M2 & M3;
-- Node name is ':8' = 'DIN_LATCH4'
-- Equation name is 'DIN_LATCH4', location is LC7_A8, type is buried.
DIN_LATCH4 = DFFE( _EQ005, WR, VCC, VCC, VCC);
_EQ005 = !_LC1_A5 & M4
# _LC1_A5 & !M4;
-- Node name is ':7' = 'DIN_LATCH5'
-- Equation name is 'DIN_LATCH5', location is LC1_A12, type is buried.
DIN_LATCH5 = DFFE( _EQ006, WR, VCC, VCC, VCC);
_EQ006 = _LC1_A5 & M4 & !M5
# !M4 & M5
# !_LC1_A5 & M5;
-- Node name is ':6' = 'DIN_LATCH6'
-- Equation name is 'DIN_LATCH6', location is LC2_A12, type is buried.
DIN_LATCH6 = DFFE( _EQ007, WR, VCC, VCC, VCC);
_EQ007 = _LC1_A5 & M4 & M5 & !M6
# !M4 & M6
# !_LC1_A5 & M6
# !M5 & M6;
-- Node name is ':27' = 'LED'
-- Equation name is 'LED', location is LC4_A15, type is buried.
LED = DFFE( _EQ008, CLKK, VCC, VCC, VCC);
_EQ008 = !time3~713
# _LC2_A15
# !time4~713;
-- Node name is ':42' = 'M0'
-- Equation name is 'M0', location is LC1_A8, type is buried.
M0 = DFFE( _EQ009, WR, VCC, VCC, VCC);
_EQ009 = _LC6_A12 & !M0;
-- Node name is ':41' = 'M1'
-- Equation name is 'M1', location is LC5_A5, type is buried.
M1 = DFFE( _EQ010, WR, VCC, VCC, VCC);
_EQ010 = _LC6_A12 & M0 & !M1
# _LC6_A12 & !M0 & M1;
-- Node name is ':40' = 'M2'
-- Equation name is 'M2', location is LC7_A5, type is buried.
M2 = DFFE( _EQ011, WR, VCC, VCC, VCC);
_EQ011 = _LC6_A12 & !M0 & M2
# _LC6_A12 & !M1 & M2
# _LC6_A12 & M0 & M1 & !M2;
-- Node name is ':39' = 'M3'
-- Equation name is 'M3', location is LC4_A5, type is buried.
M3 = DFFE( _EQ012, WR, VCC, VCC, VCC);
_EQ012 = _LC3_A5 & _LC6_A12;
-- Node name is ':38' = 'M4'
-- Equation name is 'M4', location is LC5_A12, type is buried.
M4 = DFFE( _EQ013, WR, VCC, VCC, VCC);
_EQ013 = !_LC1_A5 & _LC6_A12 & M4
# _LC1_A5 & _LC6_A12 & !M4;
-- Node name is ':37' = 'M5'
-- Equation name is 'M5', location is LC8_A12, type is buried.
M5 = DFFE( _EQ014, WR, VCC, VCC, VCC);
_EQ014 = _LC6_A12 & !M4 & M5
# !_LC1_A5 & _LC6_A12 & M5
# _LC1_A5 & _LC6_A12 & M4 & !M5;
-- Node name is ':36' = 'M6'
-- Equation name is 'M6', location is LC7_A12, type is buried.
M6 = DFFE( _EQ015, WR, VCC, VCC, VCC);
_EQ015 = _LC3_A12 & _LC4_A12;
-- Node name is ':341' = 'SCIT_V0'
-- Equation name is 'SCIT_V0', location is LC7_A9, type is buried.
SCIT_V0 = DFFE( _EQ016, CLKK, VCC, VCC, VCC);
_EQ016 = _LC4_A9 & !SCIT_V0;
-- Node name is ':340' = 'SCIT_V1'
-- Equation name is 'SCIT_V1', location is LC6_A9, type is buried.
SCIT_V1 = DFFE( _EQ017, CLKK, VCC, VCC, VCC);
_EQ017 = _LC4_A9 & SCIT_V0 & !SCIT_V1
# _LC4_A9 & !SCIT_V0 & SCIT_V1;
-- Node name is ':339' = 'SCIT_V2'
-- Equation name is 'SCIT_V2', location is LC3_A1, type is buried.
SCIT_V2 = DFFE( _EQ018, CLKK, VCC, VCC, VCC);
_EQ018 = !_LC1_A9 & _LC4_A9 & SCIT_V2
# _LC1_A9 & _LC4_A9 & !SCIT_V2
# _LC5_A1;
-- Node name is ':338' = 'SCIT_V3'
-- Equation name is 'SCIT_V3', location is LC8_A1, type is buried.
SCIT_V3 = DFFE( _EQ019, CLKK, VCC, VCC, VCC);
_EQ019 = _LC4_A9 & !_LC7_A1 & SCIT_V3
# _LC4_A9 & _LC7_A1 & !SCIT_V3
# _LC5_A1;
-- Node name is ':337' = 'SCIT_V4'
-- Equation name is 'SCIT_V4', location is LC4_A1, type is buried.
SCIT_V4 = DFFE( _EQ020, CLKK, VCC, VCC, VCC);
_EQ020 = !_LC2_A1 & _LC4_A9 & SCIT_V4
# _LC2_A1 & _LC4_A9 & !SCIT_V4
# _LC5_A1;
-- Node name is ':336' = 'SCIT_V5'
-- Equation name is 'SCIT_V5', location is LC6_A1, type is buried.
SCIT_V5 = DFFE( _EQ021, CLKK, VCC, VCC, VCC);
_EQ021 = !SCIT_V4 & SCIT_V5
# !_LC2_A1 & SCIT_V5
# _LC2_A1 & _LC2_A9 & SCIT_V4 & !SCIT_V5;
-- Node name is ':955' = 'time0~713'
-- Equation name is 'time0~713', location is LC5_A15, type is buried.
time0~713 = DFFE( _EQ022, CLKK, VCC, VCC, VCC);
_EQ022 = _LC1_A15 & !time0~713;
-- Node name is ':837' = 'time0'
-- Equation name is 'time0', location is LC5_A11, type is buried.
time0 = DFFE( _EQ023, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = _LC3_A11 & !time0;
-- Node name is ':954' = 'time1~713'
-- Equation name is 'time1~713', location is LC3_A15, type is buried.
time1~713 = DFFE( _EQ024, CLKK, VCC, VCC, VCC);
_EQ024 = _LC1_A15 & time0~713 & !time1~713
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