max232.vhd

这是FPGA系统的一个简单的与上位机串行通讯的的小程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY MAX232 IS
   PORT (
      AD_RAM_LED:              OUT STD_LOGIC;
      clk                     : IN std_Ulogic;   
      txd                     : OUT std_Ulogic --串行数据发送端        
      );
END MAX232;

ARCHITECTURE arch OF MAX232 IS
SIGNAL SCIT :            std_Ulogic_vector(5 DOWNTO 0);
SIGNAL Sh_T :            std_Ulogic_vector(3 DOWNTO 0);
SIGNAL SL_T :            std_Ulogic_vector(1 DOWNTO 0);
SIGNAL D_FB :            std_Ulogic_vector(7 DOWNTO 0);
SIGNAL DIN_LATCH :       std_Ulogic_vector(7 DOWNTO 0);
SIGNAL DO_LATCH :        std_Ulogic_vector(7 DOWNTO 0);
SIGNAL TXDF,WR :            std_Ulogic;
SIGNAL LED                :STD_LOGIC;
SIGNAL CLKK                :STD_LOGIC;
BEGIN
AD_RAM_LED<=LED;
SH_T <= SCIT(5 DOWNTO 2);
SL_T <= SCIT(1 DOWNTO 0);

PROCESS (WR)
VARIABLE M : INTEGER RANGE 0 TO 100 :=0;
VARIABLE DATA_V : std_logic_vector(7 DOWNTO 0);
BEGIN
 IF(WR'EVENT AND WR = '1') THEN
 
       M := M+1;
       DATA_V := CONV_STD_LOGIC_VECTOR(M,6);
       DIN_LATCH <= TO_STDULOGICVECTOR(DATA_V);
       IF M>=100 THEN M  :=0;
       END IF;

 END IF;
END PROCESS;

PROCESS(CLKK,WR)
BEGIN
IF( WR ='0')THEN
 TXDF <= '0';
ELSIF(CLKK'EVENT AND CLKK = '1') THEN
    IF((TXDF='0')AND(SH_T="1111")AND(SL_T="11")) THEN
          TXDF <= '1';
    END IF;
END IF;

END PROCESS;

PROCESS(CLKK)
VARIABLE SCIT_V : INTEGER RANGE 0 TO 63;
VARIABLE SCIT_S : std_logic_vector(5 DOWNTO 0);
BEGIN
IF(CLKK'EVENT AND CLKK = '1') THEN
     IF(SCIT_V <= 27)THEN                 --IF SCIT_V="011011"
        IF(TXDF = '0'AND WR = '1')THEN 
           SCIT_V := 28;                 -- SCIT_V="011100"
         ELSE
           SCIT_V := 0;
         END IF;
     ELSE
         SCIT_V := SCIT_V + 1;
     END IF;
END IF;
SCIT_S := CONV_STD_LOGIC_VECTOR(SCIT_V,6);
SCIT <= TO_STDULOGICVECTOR(SCIT_S);

END PROCESS;

PROCESS ( SH_T)
 BEGIN
   CASE SH_T IS
      WHEN "0111" => TXD<='0';
      WHEN "1000" => TXD<=DIN_LATCH(0);
      WHEN "1001" => TXD<=DIN_LATCH(1);
      WHEN "1010" => TXD<=DIN_LATCH(2);
      WHEN "1011" => TXD<=DIN_LATCH(3);
      WHEN "1100" => TXD<=DIN_LATCH(4);
      WHEN "1101" => TXD<=DIN_LATCH(5);
      WHEN "1110" => TXD<=DIN_LATCH(6);
      WHEN "1111" => TXD<=DIN_LATCH(7);
      WHEN OTHERS => TXD<='1';
   END CASE;
END PROCESS;

PROCESS(CLK)
VARIABLE time : integer range 0 to 24 :=0; 
BEGIN
  IF CLK'EVENT AND CLK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 24 THEN 
        TIME := 0;  
        CLKK <= not CLKK;
       END IF;
       END IF;       
end process;

PROCESS(CLKK)
VARIABLE time : integer range 0 to 25 :=0; 
BEGIN
  IF CLKK'EVENT AND CLKK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 25 THEN 
        TIME := 0;  
        WR <= not WR;
         LED <= '0';
        ELSE LED <= '1';
       END IF;
       END IF;
       
end process;

END arch;