📄 max232.rpt
字号:
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\myproject22\max232.rpt
max232
** CLOCK SIGNALS **
Type Fan-out Name
DFF 19 WR
DFF 15 CLKK0
INPUT 14 clk
DFF 14 CLKK
INPUT 8 clk1
INPUT 4 LOAD
Device-Specific Information: c:\myproject22\max232.rpt
max232
** CLEAR SIGNALS **
Type Fan-out Name
DFF 43 A
DFF 19 WR
Device-Specific Information: c:\myproject22\max232.rpt
max232
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
LOAD : INPUT;
-- Node name is ':36' = 'A'
-- Equation name is 'A', location is LC1_B16, type is buried.
A = DFFE(!A, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is 'AD_RAM_LED1'
-- Equation name is 'AD_RAM_LED1', type is output
AD_RAM_LED1 = TXDLED;
-- Node name is 'AD_RAM_LED2'
-- Equation name is 'AD_RAM_LED2', type is output
AD_RAM_LED2 = VCC;
-- Node name is 'AD_RAM_LED3'
-- Equation name is 'AD_RAM_LED3', type is output
AD_RAM_LED3 = VCC;
-- Node name is 'AD_RAM_LED4'
-- Equation name is 'AD_RAM_LED4', type is output
AD_RAM_LED4 = VCC;
-- Node name is ':91' = 'CLKK'
-- Equation name is 'CLKK', location is LC4_B14, type is buried.
CLKK = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = CLKK & _LC4_B15 & time3~1143
# CLKK & !_LC4_B15 & !time3~1143
# CLKK & !time3~1143 & !time4~1143
# CLKK & !_LC4_B15 & !time4~1143
# !CLKK & _LC4_B15 & !time3~1143 & time4~1143
# !CLKK & !_LC4_B15 & time3~1143 & time4~1143;
-- Node name is ':104' = 'CLKK0'
-- Equation name is 'CLKK0', location is LC5_C5, type is buried.
CLKK0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = CLKK0 & _LC1_C5
# CLKK0 & !_LC2_C5
# !CLKK0 & !_LC1_C5 & _LC2_C5;
-- Node name is 'CS'
-- Equation name is 'CS', type is output
CS = GND;
-- Node name is ':77' = 'DIN_LATCH0'
-- Equation name is 'DIN_LATCH0', location is LC5_B19, type is buried.
DIN_LATCH0 = DFFE( _EQ003, WR, VCC, VCC, VCC);
_EQ003 = A & DIN_LATCH0
# !A & D0;
-- Node name is ':76' = 'DIN_LATCH1'
-- Equation name is 'DIN_LATCH1', location is LC6_B19, type is buried.
DIN_LATCH1 = DFFE( _EQ004, WR, VCC, VCC, VCC);
_EQ004 = A & DIN_LATCH1
# !A & D1;
-- Node name is ':75' = 'DIN_LATCH2'
-- Equation name is 'DIN_LATCH2', location is LC3_B24, type is buried.
DIN_LATCH2 = DFFE( _EQ005, WR, VCC, VCC, VCC);
_EQ005 = A & DIN_LATCH2
# !A & D2;
-- Node name is ':74' = 'DIN_LATCH3'
-- Equation name is 'DIN_LATCH3', location is LC4_B24, type is buried.
DIN_LATCH3 = DFFE( _EQ006, WR, VCC, VCC, VCC);
_EQ006 = A & DIN_LATCH3
# !A & D3;
-- Node name is ':73' = 'DIN_LATCH4'
-- Equation name is 'DIN_LATCH4', location is LC4_B19, type is buried.
DIN_LATCH4 = DFFE( _EQ007, WR, VCC, VCC, VCC);
_EQ007 = A & DIN_LATCH4
# !A & D4;
-- Node name is ':72' = 'DIN_LATCH5'
-- Equation name is 'DIN_LATCH5', location is LC4_B13, type is buried.
DIN_LATCH5 = DFFE( _EQ008, WR, VCC, VCC, VCC);
_EQ008 = A & DIN_LATCH5
# !A & D5;
-- Node name is ':71' = 'DIN_LATCH6'
-- Equation name is 'DIN_LATCH6', location is LC2_B13, type is buried.
DIN_LATCH6 = DFFE( _EQ009, WR, VCC, VCC, VCC);
_EQ009 = A & DIN_LATCH6
# !A & D6;
-- Node name is ':70' = 'DIN_LATCH7'
-- Equation name is 'DIN_LATCH7', location is LC5_B13, type is buried.
DIN_LATCH7 = DFFE( _EQ010, WR, VCC, VCC, VCC);
_EQ010 = A & DIN_LATCH7
# !A & D7;
-- Node name is 'DIR'
-- Equation name is 'DIR', type is output
DIR = _LC8_C14;
-- Node name is 'DR0'
-- Equation name is 'DR0', type is output
DR0 = _LC8_B19;
-- Node name is 'DR1'
-- Equation name is 'DR1', type is output
DR1 = _LC2_A18;
-- Node name is 'DR2'
-- Equation name is 'DR2', type is output
DR2 = _LC8_A23;
-- Node name is 'DR3'
-- Equation name is 'DR3', type is output
DR3 = _LC1_B2;
-- Node name is 'DR4'
-- Equation name is 'DR4', type is output
DR4 = _LC4_B6;
-- Node name is 'DR5'
-- Equation name is 'DR5', type is output
DR5 = _LC1_B21;
-- Node name is 'DR6'
-- Equation name is 'DR6', type is output
DR6 = _LC1_A19;
-- Node name is 'DR7'
-- Equation name is 'DR7', type is output
DR7 = _LC8_B20;
-- Node name is 'DR8'
-- Equation name is 'DR8', type is output
DR8 = GND;
-- Node name is 'DR9'
-- Equation name is 'DR9', type is output
DR9 = GND;
-- Node name is 'DR10'
-- Equation name is 'DR10', type is output
DR10 = GND;
-- Node name is 'DR11'
-- Equation name is 'DR11', type is output
DR11 = GND;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(TIME0, VCC);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(TIME1, VCC);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(TIME2, VCC);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(TIME3, VCC);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(TIME4, VCC);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(TIME5, VCC);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(TIME6, VCC);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(TIME7, VCC);
-- Node name is 'OE'
-- Equation name is 'OE', type is output
OE = _LC7_C13;
-- Node name is ':1371' = 'SCIT_V0'
-- Equation name is 'SCIT_V0', location is LC4_B16, type is buried.
SCIT_V0 = DFFE( _EQ011, CLKK, !A, VCC, VCC);
_EQ011 = _LC1_B18 & !SCIT_V0;
-- Node name is ':1370' = 'SCIT_V1'
-- Equation name is 'SCIT_V1', location is LC3_B16, type is buried.
SCIT_V1 = DFFE( _EQ012, CLKK, !A, VCC, VCC);
_EQ012 = _LC1_B18 & SCIT_V0 & !SCIT_V1
# _LC1_B18 & !SCIT_V0 & SCIT_V1;
-- Node name is ':1369' = 'SCIT_V2'
-- Equation name is 'SCIT_V2', location is LC3_B22, type is buried.
SCIT_V2 = DFFE( _EQ013, CLKK, !A, VCC, VCC);
_EQ013 = _LC1_B18 & !_LC2_B16 & SCIT_V2
# _LC1_B18 & _LC2_B16 & !SCIT_V2
# _LC7_B22;
-- Node name is ':1368' = 'SCIT_V3'
-- Equation name is 'SCIT_V3', location is LC5_B22, type is buried.
SCIT_V3 = DFFE( _EQ014, CLKK, !A, VCC, VCC);
_EQ014 = _LC1_B18 & !_LC8_B22 & SCIT_V3
# _LC1_B18 & _LC8_B22 & !SCIT_V3
# _LC7_B22;
-- Node name is ':1367' = 'SCIT_V4'
-- Equation name is 'SCIT_V4', location is LC1_B22, type is buried.
SCIT_V4 = DFFE( _EQ015, CLKK, !A, VCC, VCC);
_EQ015 = _LC1_B18 & !_LC6_B22 & SCIT_V4
# _LC1_B18 & _LC6_B22 & !SCIT_V4
# _LC7_B22;
-- Node name is ':1366' = 'SCIT_V5'
-- Equation name is 'SCIT_V5', location is LC2_B22, type is buried.
SCIT_V5 = DFFE( _EQ016, CLKK, !A, VCC, VCC);
_EQ016 = !SCIT_V4 & SCIT_V5
# !_LC6_B22 & SCIT_V5
# _LC1_B13 & _LC6_B22 & SCIT_V4 & !SCIT_V5;
-- Node name is ':562' = 'TIME0~549'
-- Equation name is 'TIME0~549', location is LC2_B19, type is buried.
TIME0~549 = DFFE( _EQ017, WR, VCC, VCC, VCC);
_EQ017 = !A & !TIME0~549;
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