📄 max232.rpt
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Total flipflops required: 69
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 14/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 8 8 1 1 8 8 8 1 0 46/0
B: 0 1 0 0 0 1 0 0 0 0 0 0 0 8 8 4 4 8 2 7 1 1 8 8 7 68/0
C: 0 0 0 0 7 8 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 18/0
Total: 0 1 0 0 7 9 0 0 0 0 0 0 0 12 9 4 12 16 4 8 9 9 16 9 7 132/0
Device-Specific Information: c:\myproject22\max232.rpt
max232
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
43 - - - -- INPUT G 0 0 0 0 clk1
53 - - - 20 BIDIR 0 1 0 1 D0
71 - - A -- BIDIR 0 1 0 1 D1
70 - - A -- BIDIR 0 1 0 1 D2
25 - - B -- BIDIR 0 1 0 1 D3
24 - - B -- BIDIR 0 1 0 1 D4
64 - - B -- BIDIR 0 1 0 1 D5
73 - - A -- BIDIR 0 1 0 1 D6
22 - - B -- BIDIR 0 1 0 1 D7
2 - - - -- INPUT G 0 0 0 0 LOAD
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\myproject22\max232.rpt
max232
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- OUTPUT 0 1 0 0 AD_RAM_LED1
54 - - - 21 OUTPUT 0 0 0 0 AD_RAM_LED2
49 - - - 16 OUTPUT 0 0 0 0 AD_RAM_LED3
30 - - C -- OUTPUT 0 0 0 0 AD_RAM_LED4
50 - - - 17 OUTPUT 0 0 0 0 CS
59 - - C -- OUTPUT 0 1 0 0 DIR
52 - - - 19 OUTPUT 0 1 0 0 DR0
72 - - A -- OUTPUT 0 1 0 0 DR1
69 - - A -- OUTPUT 0 1 0 0 DR2
21 - - B -- OUTPUT 0 1 0 0 DR3
23 - - B -- OUTPUT 0 1 0 0 DR4
67 - - B -- OUTPUT 0 1 0 0 DR5
16 - - A -- OUTPUT 0 1 0 0 DR6
65 - - B -- OUTPUT 0 1 0 0 DR7
9 - - - 02 OUTPUT 0 0 0 0 DR8
79 - - - 24 OUTPUT 0 0 0 0 DR9
7 - - - 03 OUTPUT 0 0 0 0 DR10
80 - - - 23 OUTPUT 0 0 0 0 DR11
53 - - - 20 TRI 0 1 0 1 D0
71 - - A -- TRI 0 1 0 1 D1
70 - - A -- TRI 0 1 0 1 D2
25 - - B -- TRI 0 1 0 1 D3
24 - - B -- TRI 0 1 0 1 D4
64 - - B -- TRI 0 1 0 1 D5
73 - - A -- TRI 0 1 0 1 D6
22 - - B -- TRI 0 1 0 1 D7
58 - - C -- OUTPUT 0 1 0 0 OE
66 - - B -- OUTPUT 0 1 0 0 txd
62 - - C -- OUTPUT 0 1 0 0 WE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\myproject22\max232.rpt
max232
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 21 AND2 0 2 0 1 |LPM_ADD_SUB:352|addcore:adder|:75
- 7 - A 21 AND2 0 3 0 1 |LPM_ADD_SUB:352|addcore:adder|:79
- 1 - A 21 AND2 0 4 0 4 |LPM_ADD_SUB:352|addcore:adder|:83
- 3 - A 16 AND2 0 2 0 1 |LPM_ADD_SUB:352|addcore:adder|:87
- 4 - A 16 AND2 0 3 0 1 |LPM_ADD_SUB:352|addcore:adder|:91
- 8 - A 16 AND2 0 4 0 1 |LPM_ADD_SUB:352|addcore:adder|:95
- 5 - B 23 AND2 0 2 0 1 |LPM_ADD_SUB:657|addcore:adder|:75
- 7 - B 23 AND2 0 3 0 1 |LPM_ADD_SUB:657|addcore:adder|:79
- 8 - B 23 AND2 0 4 0 4 |LPM_ADD_SUB:657|addcore:adder|:83
- 1 - B 17 AND2 0 2 0 1 |LPM_ADD_SUB:657|addcore:adder|:87
- 6 - B 17 AND2 0 3 0 1 |LPM_ADD_SUB:657|addcore:adder|:91
- 7 - B 17 AND2 0 4 0 1 |LPM_ADD_SUB:657|addcore:adder|:95
- 2 - B 16 AND2 0 2 0 4 |LPM_ADD_SUB:1490|addcore:adder|:67
- 8 - B 22 AND2 0 2 0 1 |LPM_ADD_SUB:1490|addcore:adder|:71
- 6 - B 22 AND2 0 3 0 2 |LPM_ADD_SUB:1490|addcore:adder|:75
- 4 - B 15 AND2 0 3 0 4 |LPM_ADD_SUB:1886|addcore:adder|:67
- 3 - C 06 AND2 0 3 0 3 |LPM_ADD_SUB:2130|addcore:adder|:125
- 2 - C 06 AND2 0 2 0 4 |LPM_ADD_SUB:2130|addcore:adder|:129
- 4 - C 06 OR2 0 3 0 1 |LPM_ADD_SUB:2130|addcore:adder|:150
- 2 - C 05 OR2 0 4 0 3 |LPM_ADD_SUB:2130|addcore:adder|:154
- 2 - A 22 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:95
- 4 - A 22 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:99
- 8 - A 22 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:103
- 1 - A 20 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:107
- 2 - A 20 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:111
- 3 - A 20 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:115
- 8 - A 20 OR2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:119
- 1 - A 17 OR2 0 4 0 3 |LPM_ADD_SUB:2465|addcore:adder|:123
- 3 - A 17 AND2 0 4 0 2 |LPM_ADD_SUB:2465|addcore:adder|:131
- 8 - C 14 DFFE + 0 1 1 0 :1
- 1 - C 18 DFFE + 0 1 1 0 :3
- 7 - C 13 DFFE + 0 1 1 0 :6
- 1 - B 16 DFFE + 0 0 0 42 A (:36)
- 5 - B 24 DFFE 0 4 0 18 WR (:69)
- 5 - B 13 DFFE 0 3 0 1 DIN_LATCH7 (:70)
- 2 - B 13 DFFE 0 3 0 1 DIN_LATCH6 (:71)
- 4 - B 13 DFFE 0 3 0 1 DIN_LATCH5 (:72)
- 4 - B 19 DFFE 0 3 0 1 DIN_LATCH4 (:73)
- 4 - B 24 DFFE 0 3 0 1 DIN_LATCH3 (:74)
- 3 - B 24 DFFE 0 3 0 1 DIN_LATCH2 (:75)
- 6 - B 19 DFFE 0 3 0 1 DIN_LATCH1 (:76)
- 5 - B 19 DFFE 0 3 0 1 DIN_LATCH0 (:77)
- 4 - B 22 DFFE 0 5 0 1 TXDF (:90)
- 4 - B 14 DFFE + 0 3 0 13 CLKK (:91)
- 5 - C 05 DFFE + 0 2 0 14 CLKK0 (:104)
- 7 - A 13 DFFE 0 3 1 0 TXDLED (:105)
- 2 - A 16 DFFE + 0 3 1 2 TIME7 (:251)
- 1 - A 16 DFFE + 0 3 1 3 TIME6 (:252)
- 6 - A 16 DFFE + 0 3 1 4 TIME5 (:253)
- 5 - A 16 DFFE + 0 3 1 5 TIME4 (:254)
- 8 - A 21 DFFE + 0 3 1 3 TIME3 (:255)
- 5 - A 21 DFFE + 0 3 1 4 TIME2 (:256)
- 4 - A 21 DFFE + 0 3 1 5 TIME1 (:257)
- 1 - B 19 DFFE + 0 1 1 6 TIME0 (:258)
- 7 - A 16 AND2 s 0 3 0 1 ~361~1
- 2 - A 21 AND2 s 0 3 0 1 ~361~2
- 3 - A 21 AND2 ! 0 4 0 7 :361
- 2 - B 17 DFFE 0 4 0 2 TIME7~549 (:555)
- 5 - B 17 DFFE 0 4 0 3 TIME6~549 (:556)
- 8 - B 17 DFFE 0 4 0 4 TIME5~549 (:557)
- 3 - B 17 DFFE 0 4 0 5 TIME4~549 (:558)
- 1 - B 23 DFFE 0 4 0 3 TIME3~549 (:559)
- 6 - B 23 DFFE 0 4 0 4 TIME2~549 (:560)
- 2 - B 23 DFFE 0 4 0 5 TIME1~549 (:561)
- 2 - B 19 DFFE 0 2 0 6 TIME0~549 (:562)
- 4 - B 17 AND2 s 0 3 0 1 ~666~1
- 3 - B 23 AND2 s 0 3 0 1 ~666~2
- 4 - B 23 AND2 ! 0 4 0 7 :666
- 8 - B 20 OR2 0 3 1 0 :1234
- 1 - A 19 OR2 0 3 1 0 :1240
- 1 - B 21 OR2 0 3 1 0 :1246
- 4 - B 06 OR2 0 3 1 0 :1252
- 1 - B 02 OR2 0 3 1 0 :1258
- 8 - A 23 OR2 0 3 1 0 :1264
- 2 - A 18 OR2 0 3 1 0 :1270
- 8 - B 19 OR2 0 3 1 0 :1276
- 2 - B 22 DFFE 0 5 0 3 SCIT_V5 (:1366)
- 1 - B 22 DFFE 0 5 0 5 SCIT_V4 (:1367)
- 5 - B 22 DFFE 0 5 0 3 SCIT_V3 (:1368)
- 3 - B 22 DFFE 0 5 0 7 SCIT_V2 (:1369)
- 3 - B 16 DFFE 0 4 0 1 SCIT_V1 (:1370)
- 4 - B 16 DFFE 0 3 0 2 SCIT_V0 (:1371)
- 1 - B 18 OR2 0 2 0 6 :1392
- 1 - B 13 AND2 0 3 0 4 :1394
- 7 - B 22 AND2 0 3 0 3 :1513
- 4 - B 18 AND2 s ! 0 2 0 1 ~1763~1
- 1 - B 24 OR2 s 0 3 0 1 ~1861~1
- 6 - B 13 OR2 s 0 4 0 1 ~1861~2
- 3 - B 19 OR2 s 0 4 0 1 ~1861~3
- 7 - B 13 OR2 s 0 4 0 1 ~1861~4
- 8 - B 13 OR2 s 0 4 0 1 ~1861~5
- 3 - B 13 OR2 0 4 1 0 :1861
- 8 - B 14 DFFE + 0 2 0 3 time4~1143 (:1864)
- 7 - B 14 DFFE + 0 2 0 3 time3~1143 (:1865)
- 3 - B 15 DFFE + 0 3 0 1 time2~1143 (:1866)
- 1 - B 15 DFFE + 0 2 0 2 time1~1143 (:1867)
- 2 - B 15 DFFE + 0 1 0 3 time0~1143 (:1868)
- 2 - B 14 OR2 0 3 0 3 :1892
- 7 - B 24 DFFE 0 3 0 2 time4~1220 (:1982)
- 6 - B 24 DFFE 0 3 0 3 time3~1220 (:1983)
- 6 - B 14 DFFE 0 4 0 1 time2~1220 (:1984)
- 3 - B 14 DFFE 0 3 0 2 time1~1220 (:1985)
- 5 - B 14 DFFE 0 2 0 3 time0~1220 (:1986)
- 2 - B 24 OR2 0 3 0 4 :2010
- 1 - B 14 AND2 0 3 0 4 :2017
- 7 - C 05 DFFE + 0 2 0 1 time6~1297 (:2100)
- 4 - C 05 DFFE + 0 3 0 2 time5~1297 (:2101)
- 3 - C 05 DFFE + 0 2 0 3 time4~1297 (:2102)
- 8 - C 06 DFFE + 0 2 0 2 time3~1297 (:2103)
- 7 - C 06 DFFE + 0 3 0 2 time2~1297 (:2104)
- 5 - C 06 DFFE + 0 2 0 3 time1~1297 (:2105)
- 6 - C 06 DFFE + 0 1 0 4 time0~1297 (:2106)
- 6 - C 05 OR2 0 2 0 6 :2138
- 1 - C 05 OR2 0 4 0 3 :2143
- 1 - C 06 OR2 s 0 3 0 1 ~2145~1
- 5 - A 17 DFFE 0 4 0 22 time12 (:2252)
- 4 - A 17 DFFE 0 3 0 2 time11 (:2253)
- 8 - A 17 DFFE 0 4 0 2 time10 (:2254)
- 7 - A 17 DFFE 0 3 0 3 time9 (:2255)
- 2 - A 17 DFFE 0 4 0 2 time8 (:2256)
- 5 - A 20 DFFE 0 4 0 2 time7~1372 (:2257)
- 7 - A 20 DFFE 0 4 0 2 time6~1372 (:2258)
- 6 - A 20 DFFE 0 4 0 2 time5~1372 (:2259)
- 4 - A 13 DFFE 0 4 0 2 time4~1372 (:2260)
- 6 - A 22 DFFE 0 4 0 2 time3~1372 (:2261)
- 5 - A 22 DFFE 0 4 0 2 time2~1372 (:2262)
- 7 - A 22 DFFE 0 4 0 2 time1~1372 (:2263)
- 2 - A 13 DFFE 0 3 0 3 time0~1372 (:2264)
- 6 - A 17 AND2 s 0 3 0 1 ~2308~1
- 3 - A 22 OR2 0 4 0 19 :2308
- 4 - A 20 OR2 s 0 4 0 1 ~2326~1
- 1 - A 22 OR2 s 0 4 0 1 ~2326~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\myproject22\max232.rpt
max232
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 0/ 48( 0%) 20/ 48( 41%) 0/16( 0%) 4/16( 25%) 3/16( 18%)
B: 14/ 96( 14%) 2/ 48( 4%) 27/ 48( 56%) 0/16( 0%) 5/16( 31%) 4/16( 25%)
C: 0/ 96( 0%) 3/ 48( 6%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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