max232.vhd

本程序是为FPGA系统所设计的一个简单的存储和读取数据的小程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY MAX232 IS
                    GENERIC ( K : INTEGER :=255);
   PORT (
      DIR,WE,CS,OE              :OUT STD_LOGIC;
      D                         :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      DR                         :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
      clk1,clk,LOAD             : IN std_Ulogic;
      AD_RAM_LED1:              OUT STD_LOGIC;
      AD_RAM_LED2:              OUT STD_LOGIC;
      AD_RAM_LED3:              OUT STD_LOGIC;
      AD_RAM_LED4:              OUT STD_LOGIC;   
      txd                     : OUT std_Ulogic --串行数据发送端        
      );
END MAX232;

ARCHITECTURE arch OF MAX232 IS
SIGNAL SCIT :            std_Ulogic_vector(5 DOWNTO 0);
SIGNAL Sh_T :            std_Ulogic_vector(3 DOWNTO 0);
SIGNAL SL_T :            std_Ulogic_vector(1 DOWNTO 0);
SIGNAL D_FB :            std_Ulogic_vector(7 DOWNTO 0);
SIGNAL DIN_LATCH :       std_Ulogic_vector(7 DOWNTO 0);
SIGNAL DO_LATCH :        std_Ulogic_vector(7 DOWNTO 0);
SIGNAL TXDF,TXDLED,WR :            std_Ulogic;
SIGNAL LED                :STD_LOGIC;
SIGNAL CLKK,CLKK0                :STD_LOGIC;

SIGNAL A:BIT := '0';
SIGNAL DZZa:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DZZb:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DZZ:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL regl:std_logic_vector(7 downto 0);

BEGIN
AD_RAM_LED1<=TXDLED;
AD_RAM_LED2<='1';
AD_RAM_LED3<='1';
AD_RAM_LED4<='1';
SH_T <= SCIT(5 DOWNTO 2);
SL_T <= SCIT(1 DOWNTO 0);

CS<='0';
DR<=DZZ ;


PROCESS( Load ) 
VARIABLE T : integer range 0 to 1 :=0;                  
BEGIN 
 IF ( Load'EVENT AND Load='1' )THEN 
       IF T = 0 THEN
       A <= '1';
       WE<='0';DIR<='1';OE<='1'; 
       ELSE 
       A <= '0';
       WE<='1';DIR<='0';OE<='0'; 
       END IF;
       IF T >= 1 THEN 
       T := 0;
       ELSE  T :=  1;
       END IF;     
 END IF;
end process;


PROCESS(CLK1,A)
VARIABLE TIME : integer range 0 to K :=0;
  
BEGIN
     DZZA <= CONV_STD_LOGIC_VECTOR (TIME,12);
     regl <= CONV_STD_LOGIC_VECTOR (TIME,8);
     D<=regl ;
     IF clk1'EVENT AND clk1='1'THEN       
         IF A = '1' THEN 
            TIME := TIME + 1;
            IF TIME >= K THEN
            TIME := K; 
            END IF;
         ELSE TIME := 0;
         END IF;
    END IF;
end process;


PROCESS (WR)
VARIABLE DATA_V : std_logic_vector(7 DOWNTO 0);
VARIABLE TIME : integer range 0 to K :=0;
BEGIN
     DZZB <= CONV_STD_LOGIC_VECTOR (TIME,12);
      IF( WR'EVENT AND WR = '1') THEN
       IF A = '0' THEN
          TIME := TIME + 1;
          IF TIME >= K THEN
          TIME := K; 
          ELSE  
          END IF;
         DATA_V := D;
         DIN_LATCH <= TO_STDULOGICVECTOR(DATA_V);
        ELSE TIME := 0;
       END IF; 
     END IF;   
END PROCESS;

PROCESS (A,DZZA,DZZB)
BEGIN
    IF( A='1')THEN
      DZZ<=DZZA;
      ELSE
      DZZ<=DZZB;
    END IF;
END PROCESS;

PROCESS(CLKK,WR)
BEGIN
IF( WR ='0')THEN
 TXDF <= '0';
ELSIF(CLKK'EVENT AND CLKK = '1') THEN
IF(((TXDF='0')AND(SH_T="1111")AND(SL_T="11")) OR A = '1') THEN
          TXDF <= '1';
    END IF;
END IF;

END PROCESS;

PROCESS(CLKK)
VARIABLE SCIT_V : INTEGER RANGE 0 TO 63;
VARIABLE SCIT_S : std_logic_vector(5 DOWNTO 0);
BEGIN
IF A ='1'THEN
  SCIT_V :=0;
ELSIF(CLKK'EVENT AND CLKK = '1') THEN
     IF(SCIT_V <= 27)THEN                 --IF SCIT_V="011011"
        IF(TXDF = '0'AND WR = '1')THEN 
           SCIT_V := 28;                 -- SCIT_V="011100"
         ELSE
           SCIT_V := 0;
         END IF;
     ELSE
         SCIT_V := SCIT_V + 1;
     END IF;
END IF;
SCIT_S := CONV_STD_LOGIC_VECTOR(SCIT_V,6);
SCIT <= TO_STDULOGICVECTOR(SCIT_S);
END PROCESS;

PROCESS ( SH_T)
 BEGIN
   CASE SH_T IS
      WHEN "0111" => TXD<='0';
      WHEN "1000" => TXD<=DIN_LATCH(0);
      WHEN "1001" => TXD<=DIN_LATCH(1);
      WHEN "1010" => TXD<=DIN_LATCH(2);
      WHEN "1011" => TXD<=DIN_LATCH(3);
      WHEN "1100" => TXD<=DIN_LATCH(4);
      WHEN "1101" => TXD<=DIN_LATCH(5);
      WHEN "1110" => TXD<=DIN_LATCH(6);
      WHEN "1111" => TXD<=DIN_LATCH(7);
      WHEN OTHERS => TXD<='1';
   END CASE;
END PROCESS;

PROCESS(CLK)
VARIABLE time : integer range 0 to 24 :=0; 
BEGIN
  IF CLK'EVENT AND CLK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 24 THEN 
        TIME := 0;  
        CLKK <= not CLKK;
       END IF;
       END IF;       
end process;

PROCESS(CLKK)
VARIABLE time : integer range 0 to 25 :=0; 
BEGIN
  IF CLKK'EVENT AND CLKK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 25 THEN 
        TIME := 0;  
        WR <= not WR;
        ELSE 
       END IF;
       END IF;
       
end process;


PROCESS(CLK)
VARIABLE time : integer range 0 to 100 :=0; 
BEGIN
  IF CLK'EVENT AND CLK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 100 THEN 
        TIME := 0;  
        CLKK0 <= not CLKK0;
       END IF;
       END IF;       
end process;
PROCESS(CLKK0)
VARIABLE time : integer range 0 to 4608 :=0; 
BEGIN
  IF CLKK0'EVENT AND CLKK0='1'THEN       
       IF TIME >= 4607 THEN 
        TIME := 0;  
         TXDLED<= not TXDLED;
       END IF;
     TIME := TIME + 1;
       END IF;
end process;

END arch;