xccpld_timesim.vhd

通过PC104访问内存地址

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: xccpld_timesim.vhd
-- /___/   /\     Timestamp: Wed Jan 09 17:12:10 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim xccpld.nga xccpld_timesim.vhd 
-- Device: XC9536-10-VQ44 (Speed File: Version 3.0)
-- Design Name: xccpld.nga
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity xccpld is
  port (
    IRQ9 : in STD_LOGIC := 'X'; 
    SMEMR : in STD_LOGIC := 'X'; 
    RESET : in STD_LOGIC := 'X'; 
    SMEMW : in STD_LOGIC := 'X'; 
    ALE : out STD_LOGIC; 
    CS : out STD_LOGIC; 
    IRQ : out STD_LOGIC; 
    RD : out STD_LOGIC; 
    RST : out STD_LOGIC; 
    WR : out STD_LOGIC; 
    DEFSUP : out STD_LOGIC; 
    A : in STD_LOGIC_VECTOR ( 19 downto 9 ) 
  );
end xccpld;

architecture Structure of xccpld is
  signal A_19_IBUF : STD_LOGIC; 
  signal A_18_IBUF : STD_LOGIC; 
  signal A_15_IBUF : STD_LOGIC; 
  signal A_12_IBUF : STD_LOGIC; 
  signal A_9_IBUF : STD_LOGIC; 
  signal A_13_IBUF : STD_LOGIC; 
  signal A_11_IBUF : STD_LOGIC; 
  signal A_10_IBUF : STD_LOGIC; 
  signal A_14_IBUF : STD_LOGIC; 
  signal A_16_IBUF : STD_LOGIC; 
  signal A_17_IBUF : STD_LOGIC; 
  signal IRQ_OBUF : STD_LOGIC; 
  signal RD_OBUF : STD_LOGIC; 
  signal RESET_IBUF : STD_LOGIC; 
  signal WR_OBUF : STD_LOGIC; 
  signal ALE_OBUF_Q : STD_LOGIC; 
  signal CS_OBUF : STD_LOGIC; 
  signal IRQ_OBUF_BUF0 : STD_LOGIC; 
  signal RD_OBUF_BUF0 : STD_LOGIC; 
  signal RST_OBUF : STD_LOGIC; 
  signal WR_OBUF_BUF0 : STD_LOGIC; 
  signal DEFSUP_OBUF : STD_LOGIC; 
  signal ALE_OBUF_Q_0 : STD_LOGIC; 
  signal ALE_OBUF_D : STD_LOGIC; 
  signal ALE_OBUF_D1 : STD_LOGIC; 
  signal ALE_OBUF_D2 : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal CS_OBUF_Q : STD_LOGIC; 
  signal CS_OBUF_D : STD_LOGIC; 
  signal CS_OBUF_D1 : STD_LOGIC; 
  signal CS_OBUF_D2 : STD_LOGIC; 
  signal IRQ_OBUF_BUF0_Q : STD_LOGIC; 
  signal IRQ_OBUF_BUF0_D : STD_LOGIC; 
  signal IRQ_OBUF_BUF0_D1 : STD_LOGIC; 
  signal IRQ_OBUF_BUF0_D2 : STD_LOGIC; 
  signal RD_OBUF_BUF0_Q : STD_LOGIC; 
  signal RD_OBUF_BUF0_D : STD_LOGIC; 
  signal RD_OBUF_BUF0_D1 : STD_LOGIC; 
  signal RD_OBUF_BUF0_D2 : STD_LOGIC; 
  signal RST_OBUF_Q : STD_LOGIC; 
  signal RST_OBUF_D : STD_LOGIC; 
  signal RST_OBUF_D1 : STD_LOGIC; 
  signal RST_OBUF_D2 : STD_LOGIC; 
  signal WR_OBUF_BUF0_Q : STD_LOGIC; 
  signal WR_OBUF_BUF0_D : STD_LOGIC; 
  signal WR_OBUF_BUF0_D1 : STD_LOGIC; 
  signal WR_OBUF_BUF0_D2 : STD_LOGIC; 
  signal DEFSUP_OBUF_Q : STD_LOGIC; 
  signal DEFSUP_OBUF_D : STD_LOGIC; 
  signal DEFSUP_OBUF_D1 : STD_LOGIC; 
  signal DEFSUP_OBUF_D2 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_ALE_OBUF_D2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_CS_OBUF_D2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_RST_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_RST_OBUF_D2_IN1 : STD_LOGIC; 
begin
  A_19_IBUF_1 : X_BUF
    port map (
      I => A(19),
      O => A_19_IBUF
    );
  A_18_IBUF_2 : X_BUF
    port map (
      I => A(18),
      O => A_18_IBUF
    );
  A_15_IBUF_3 : X_BUF
    port map (
      I => A(15),
      O => A_15_IBUF
    );
  A_12_IBUF_4 : X_BUF
    port map (
      I => A(12),
      O => A_12_IBUF
    );
  A_9_IBUF_5 : X_BUF
    port map (
      I => A(9),
      O => A_9_IBUF
    );
  A_13_IBUF_6 : X_BUF
    port map (
      I => A(13),
      O => A_13_IBUF
    );
  A_11_IBUF_7 : X_BUF
    port map (
      I => A(11),
      O => A_11_IBUF
    );
  A_10_IBUF_8 : X_BUF
    port map (
      I => A(10),
      O => A_10_IBUF
    );
  A_14_IBUF_9 : X_BUF
    port map (
      I => A(14),
      O => A_14_IBUF
    );
  A_16_IBUF_10 : X_BUF
    port map (
      I => A(16),
      O => A_16_IBUF
    );
  A_17_IBUF_11 : X_BUF
    port map (
      I => A(17),
      O => A_17_IBUF
    );
  IRQ_OBUF_12 : X_BUF
    port map (
      I => IRQ9,
      O => IRQ_OBUF
    );
  RD_OBUF_13 : X_BUF
    port map (
      I => SMEMR,
      O => RD_OBUF
    );
  RESET_IBUF_14 : X_BUF
    port map (
      I => RESET,
      O => RESET_IBUF
    );
  WR_OBUF_15 : X_BUF
    port map (
      I => SMEMW,
      O => WR_OBUF
    );
  ALE_16 : X_BUF
    port map (
      I => ALE_OBUF_Q,
      O => ALE
    );
  CS_17 : X_BUF
    port map (
      I => CS_OBUF,
      O => CS
    );
  IRQ_18 : X_BUF
    port map (
      I => IRQ_OBUF_BUF0,
      O => IRQ
    );
  RD_19 : X_BUF
    port map (
      I => RD_OBUF_BUF0,
      O => RD
    );
  RST_20 : X_BUF
    port map (
      I => RST_OBUF,
      O => RST
    );
  WR_21 : X_BUF
    port map (
      I => WR_OBUF_BUF0,
      O => WR
    );
  DEFSUP_22 : X_BUF
    port map (
      I => DEFSUP_OBUF,
      O => DEFSUP
    );
  ALE_OBUF_Q_23 : X_BUF
    port map (
      I => ALE_OBUF_Q_0,
      O => ALE_OBUF_Q
    );
  ALE_OBUF_Q_24 : X_BUF
    port map (
      I => ALE_OBUF_D,
      O => ALE_OBUF_Q_0
    );
  ALE_OBUF_D_25 : X_XOR2
    port map (
      I0 => ALE_OBUF_D1,
      I1 => ALE_OBUF_D2,
      O => ALE_OBUF_D
    );
  ALE_OBUF_D1_26 : X_ZERO
    port map (
      O => ALE_OBUF_D1
    );
  ALE_OBUF_D2_27 : X_AND16
    port map (
      I0 => A_19_IBUF,
      I1 => A_18_IBUF,
      I2 => A_15_IBUF,
      I3 => A_12_IBUF,
      I4 => NlwInverterSignal_ALE_OBUF_D2_IN4,
      I5 => NlwInverterSignal_ALE_OBUF_D2_IN5,
      I6 => NlwInverterSignal_ALE_OBUF_D2_IN6,
      I7 => NlwInverterSignal_ALE_OBUF_D2_IN7,
      I8 => NlwInverterSignal_ALE_OBUF_D2_IN8,
      I9 => NlwInverterSignal_ALE_OBUF_D2_IN9,
      I10 => NlwInverterSignal_ALE_OBUF_D2_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => ALE_OBUF_D2
    );
  Vcc_28 : X_ONE
    port map (
      O => Vcc
    );
  CS_OBUF_29 : X_BUF
    port map (
      I => CS_OBUF_Q,
      O => CS_OBUF
    );
  CS_OBUF_Q_30 : X_BUF
    port map (
      I => CS_OBUF_D,
      O => CS_OBUF_Q
    );
  CS_OBUF_D_31 : X_XOR2
    port map (
      I0 => NlwInverterSignal_CS_OBUF_D_IN0,
      I1 => CS_OBUF_D2,
      O => CS_OBUF_D
    );
  CS_OBUF_D1_32 : X_ZERO
    port map (
      O => CS_OBUF_D1
    );
  CS_OBUF_D2_33 : X_AND16
    port map (
      I0 => A_19_IBUF,
      I1 => A_18_IBUF,
      I2 => A_15_IBUF,
      I3 => A_12_IBUF,
      I4 => NlwInverterSignal_CS_OBUF_D2_IN4,
      I5 => NlwInverterSignal_CS_OBUF_D2_IN5,
      I6 => NlwInverterSignal_CS_OBUF_D2_IN6,
      I7 => NlwInverterSignal_CS_OBUF_D2_IN7,
      I8 => NlwInverterSignal_CS_OBUF_D2_IN8,
      I9 => NlwInverterSignal_CS_OBUF_D2_IN9,
      I10 => NlwInverterSignal_CS_OBUF_D2_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => CS_OBUF_D2
    );
  IRQ_OBUF_BUF0_34 : X_BUF
    port map (
      I => IRQ_OBUF_BUF0_Q,
      O => IRQ_OBUF_BUF0
    );
  IRQ_OBUF_BUF0_Q_35 : X_BUF
    port map (
      I => IRQ_OBUF_BUF0_D,
      O => IRQ_OBUF_BUF0_Q
    );
  IRQ_OBUF_BUF0_D_36 : X_XOR2
    port map (
      I0 => IRQ_OBUF_BUF0_D1,
      I1 => IRQ_OBUF_BUF0_D2,
      O => IRQ_OBUF_BUF0_D
    );
  IRQ_OBUF_BUF0_D1_37 : X_ZERO
    port map (
      O => IRQ_OBUF_BUF0_D1
    );
  IRQ_OBUF_BUF0_D2_38 : X_AND2
    port map (
      I0 => IRQ_OBUF,
      I1 => IRQ_OBUF,
      O => IRQ_OBUF_BUF0_D2
    );
  RD_OBUF_BUF0_39 : X_BUF
    port map (
      I => RD_OBUF_BUF0_Q,
      O => RD_OBUF_BUF0
    );
  RD_OBUF_BUF0_Q_40 : X_BUF
    port map (
      I => RD_OBUF_BUF0_D,
      O => RD_OBUF_BUF0_Q
    );
  RD_OBUF_BUF0_D_41 : X_XOR2
    port map (
      I0 => RD_OBUF_BUF0_D1,
      I1 => RD_OBUF_BUF0_D2,
      O => RD_OBUF_BUF0_D
    );
  RD_OBUF_BUF0_D1_42 : X_ZERO
    port map (
      O => RD_OBUF_BUF0_D1
    );
  RD_OBUF_BUF0_D2_43 : X_AND2
    port map (
      I0 => RD_OBUF,
      I1 => RD_OBUF,
      O => RD_OBUF_BUF0_D2
    );
  RST_OBUF_44 : X_BUF
    port map (
      I => RST_OBUF_Q,
      O => RST_OBUF
    );
  RST_OBUF_Q_45 : X_BUF
    port map (
      I => RST_OBUF_D,
      O => RST_OBUF_Q
    );
  RST_OBUF_D_46 : X_XOR2
    port map (
      I0 => RST_OBUF_D1,
      I1 => RST_OBUF_D2,
      O => RST_OBUF_D
    );
  RST_OBUF_D1_47 : X_ZERO
    port map (
      O => RST_OBUF_D1
    );
  RST_OBUF_D2_48 : X_AND2
    port map (
      I0 => NlwInverterSignal_RST_OBUF_D2_IN0,
      I1 => NlwInverterSignal_RST_OBUF_D2_IN1,
      O => RST_OBUF_D2
    );
  WR_OBUF_BUF0_49 : X_BUF
    port map (
      I => WR_OBUF_BUF0_Q,
      O => WR_OBUF_BUF0
    );
  WR_OBUF_BUF0_Q_50 : X_BUF
    port map (
      I => WR_OBUF_BUF0_D,
      O => WR_OBUF_BUF0_Q
    );
  WR_OBUF_BUF0_D_51 : X_XOR2
    port map (
      I0 => WR_OBUF_BUF0_D1,
      I1 => WR_OBUF_BUF0_D2,
      O => WR_OBUF_BUF0_D
    );
  WR_OBUF_BUF0_D1_52 : X_ZERO
    port map (
      O => WR_OBUF_BUF0_D1
    );
  WR_OBUF_BUF0_D2_53 : X_AND2
    port map (
      I0 => WR_OBUF,
      I1 => WR_OBUF,
      O => WR_OBUF_BUF0_D2
    );
  DEFSUP_OBUF_54 : X_BUF
    port map (
      I => DEFSUP_OBUF_Q,
      O => DEFSUP_OBUF
    );
  DEFSUP_OBUF_Q_55 : X_BUF
    port map (
      I => DEFSUP_OBUF_D,
      O => DEFSUP_OBUF_Q
    );
  DEFSUP_OBUF_D_56 : X_XOR2
    port map (
      I0 => DEFSUP_OBUF_D1,
      I1 => DEFSUP_OBUF_D2,
      O => DEFSUP_OBUF_D
    );
  DEFSUP_OBUF_D1_57 : X_ZERO
    port map (
      O => DEFSUP_OBUF_D1
    );
  DEFSUP_OBUF_D2_58 : X_ONE
    port map (
      O => DEFSUP_OBUF_D2
    );
  NlwInverterBlock_ALE_OBUF_D2_IN4 : X_INV
    port map (
      I => A_9_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN4
    );
  NlwInverterBlock_ALE_OBUF_D2_IN5 : X_INV
    port map (
      I => A_13_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN5
    );
  NlwInverterBlock_ALE_OBUF_D2_IN6 : X_INV
    port map (
      I => A_11_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN6
    );
  NlwInverterBlock_ALE_OBUF_D2_IN7 : X_INV
    port map (
      I => A_10_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN7
    );
  NlwInverterBlock_ALE_OBUF_D2_IN8 : X_INV
    port map (
      I => A_14_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN8
    );
  NlwInverterBlock_ALE_OBUF_D2_IN9 : X_INV
    port map (
      I => A_16_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN9
    );
  NlwInverterBlock_ALE_OBUF_D2_IN10 : X_INV
    port map (
      I => A_17_IBUF,
      O => NlwInverterSignal_ALE_OBUF_D2_IN10
    );
  NlwInverterBlock_CS_OBUF_D_IN0 : X_INV
    port map (
      I => CS_OBUF_D1,
      O => NlwInverterSignal_CS_OBUF_D_IN0
    );
  NlwInverterBlock_CS_OBUF_D2_IN4 : X_INV
    port map (
      I => A_9_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN4
    );
  NlwInverterBlock_CS_OBUF_D2_IN5 : X_INV
    port map (
      I => A_13_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN5
    );
  NlwInverterBlock_CS_OBUF_D2_IN6 : X_INV
    port map (
      I => A_11_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN6
    );
  NlwInverterBlock_CS_OBUF_D2_IN7 : X_INV
    port map (
      I => A_10_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN7
    );
  NlwInverterBlock_CS_OBUF_D2_IN8 : X_INV
    port map (
      I => A_14_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN8
    );
  NlwInverterBlock_CS_OBUF_D2_IN9 : X_INV
    port map (
      I => A_16_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN9
    );
  NlwInverterBlock_CS_OBUF_D2_IN10 : X_INV
    port map (
      I => A_17_IBUF,
      O => NlwInverterSignal_CS_OBUF_D2_IN10
    );
  NlwInverterBlock_RST_OBUF_D2_IN0 : X_INV
    port map (
      I => RESET_IBUF,
      O => NlwInverterSignal_RST_OBUF_D2_IN0
    );
  NlwInverterBlock_RST_OBUF_D2_IN1 : X_INV
    port map (
      I => RESET_IBUF,
      O => NlwInverterSignal_RST_OBUF_D2_IN1
    );

end Structure;