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Release 7.1i - Timing Report Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F = MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F = MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.Path tracing .....The number of paths traced: 71.The number of paths traced: 143.Checking for asynchronous logic...No asynchronous logic found.Generating TA GUI report ...Generating detailed paths report ...e:\cpld/xccpld_html/tim/timing_report.htm has been created.
Started process "Generate HTML report".Release 7.1i - CPLD HTML Report Processor H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Fit".Release 7.1i - CPLD Optimizer/Partitioner H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC9536-15-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 7 equations into 2 function blocksDesign xccpld has been optimized and fit into device XC9536-15-VQ44.
Started process "Generate Programming File".Release 7.1i - Programming File Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Started process "Generate Timing".Release 7.1i - Timing Report Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F = MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F = MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.Path tracing .....The number of paths traced: 71.The number of paths traced: 143.Checking for asynchronous logic...No asynchronous logic found.Generating TA GUI report ...Generating detailed paths report ...e:\cpld/xccpld_html/tim/timing_report.htm has been created.
Started process "Generate HTML report".Release 7.1i - CPLD HTML Report Processor H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.Entity <xccpld> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Started process "Translate".Release 7.1i - ngdbuild H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc xccpld.ucf -p xc9500 xccpld.ngc xccpld.ngd Reading NGO file 'E:/cpld/xccpld.ngc' ...Applying constraints in "xccpld.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "xccpld.ngd" ...Writing NGDBUILD log file "xccpld.bld"...NGDBUILD done.
Started process "Fit".Release 7.1i - CPLD Optimizer/Partitioner H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC9536-15-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 7 equations into 2 function blocksDesign xccpld has been optimized and fit into device XC9536-15-VQ44.
Started process "Generate Programming File".Release 7.1i - Programming File Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Started process "Generate Timing".Release 7.1i - Timing Report Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F = MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F = MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.Path tracing .....The number of paths traced: 71.The number of paths traced: 143.Checking for asynchronous logic...No asynchronous logic found.Generating TA GUI report ...Generating detailed paths report ...e:\cpld/xccpld_html/tim/timing_report.htm has been created.
Started process "Generate HTML report".Release 7.1i - CPLD HTML Report Processor H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.Entity <xccpld> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Started process "Translate".Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc xccpld.ucf -p xc9500 xccpld.ngc xccpld.ngd Reading NGO file 'E:/cpld/xccpld.ngc' ...Applying constraints in "xccpld.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "xccpld.ngd" ...Writing NGDBUILD log file "xccpld.bld"...NGDBUILD done.
Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC9536-15-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 7 equations into 2 function blocksDesign xccpld has been optimized and fit into device XC9536-15-VQ44.
Started process "Generate Programming File".Release 7.1.04i - Programming File Generator H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Started process "Generate Timing".Release 7.1.04i - Timing Report Generator H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F = MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F = MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.Path tracing .....The number of paths traced: 71.The number of paths traced: 143.Checking for asynchronous logic...No asynchronous logic found.Generating TA GUI report ...Generating detailed paths report ...e:\cpld/xccpld_html/tim/timing_report.htm has been created.
Started process "Generate HTML report".Release 7.1.04i - CPLD HTML Report Processor H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.Entity <xccpld> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================⌨️ 快捷键说明
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