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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.ERROR:HDLParsers:164 - "E:/cpld/xccpld.vhd" Line 44. parse error, unexpected END, expecting SEMICOLONWARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it.--> Total memory usage is 77028 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.ERROR:HDLParsers:164 - "E:/cpld/xccpld.vhd" Line 49. parse error, unexpected IF--> Total memory usage is 76800 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.ERROR:HDLParsers:164 - "E:/cpld/xccpld.vhd" Line 69. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACKERROR:HDLParsers:164 - "E:/cpld/xccpld.vhd" Line 70. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACKERROR:HDLParsers:164 - "E:/cpld/xccpld.vhd" Line 71. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACKWARNING:HDLParsers:1406 - "E:/cpld/xccpld.vhd" Line 49. No sensitivity list and no wait in the process--> Total memory usage is 76800 kilobytesNumber of errors : 3 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.WARNING:HDLParsers:1406 - "E:/cpld/xccpld.vhd" Line 49. No sensitivity list and no wait in the processEntity <xccpld> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <Behavioral>).WARNING:Xst:819 - "E:/cpld/xccpld.vhd" line 49: The following signals are missing in the process sensitivity list: A, AEN, IOW, IOR.Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".WARNING:Xst:1306 - Output <RST> is never assigned.WARNING:Xst:647 - Input <RESET> is never used.Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.Entity <xccpld> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Architecture behavioral of Entity xccpld is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/cpld/xccpld.vhd" in Library work.Entity <xccpld> compiled.Entity <xccpld> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xccpld> (Architecture <behavioral>).Entity <xccpld> analyzed. Unit <xccpld> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xccpld>. Related source file is "E:/cpld/xccpld.vhd".Unit <xccpld> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xccpld> ...
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Extracting independent architecture files...Release 7.1i - ngdbuild H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc xccpld.ucf -p xc9500 xccpld.ngc xccpld.ngd Reading NGO file 'E:/cpld/xccpld.ngc' ...Applying constraints in "xccpld.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "xccpld.ngd" ...Writing NGDBUILD log file "xccpld.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Fit".Release 7.1i - CPLD Optimizer/Partitioner H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC9536-5-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 7 equations into 2 function blocksDesign xccpld has been optimized and fit into device XC9536-5-VQ44.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 7.1i - Programming File Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Lock Pins".Release 7.1i - pin2ucf H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Pin Locking constraints file generated in : xccpld.ucf
Project Navigator Auto-Make Log File-------------------------------------
Started process "HDL Converter".ERROR: No input file specified for the "HDL Converter" process.Please select an input file (ABEL or AHDL) from the property menu.(Right click on the "HDL Converter" process name and select 'Properties')Process "HDL Converter" did not complete due to error(s) reported by internal script.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Timing".Release 7.1i - Timing Report Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_F2F = MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.WARNING:Cpld:997 - Error during loading TIMESPEC AUTO_TS_P2F = MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS, the timespec parser failed to find any instance/net with an expected TNM defined in TIMEGRP FFS(*). The timing constraint will be ignored.Path tracing .....The number of paths traced: 71.⌨️ 快捷键说明
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