xccpld.vhd

通过PC104访问内存地址

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-- Company: 
-- Engineer:
--
-- Create Date:    21:45:27 11/01/06
-- Design Name:    
-- Module Name:    xccpld - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:
  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity xccpld is
    Port ( A : in std_logic_vector( 19 downto 9);
	       -- AEN : in std_logic; 
           IRQ9 : in std_logic;
			 -- RESET : in std_logic;
			  SMEMW : in std_logic;
			  SMEMR : in std_logic;
			  
           RST : out std_logic;
           CS : out std_logic;
           IRQ : out std_logic;
           ALE : out std_logic;
           WR : out std_logic;
			  RD : out std_logic;
			  DEFSUP : out std_logic
			  );
end xccpld;

architecture Behavioral of xccpld is

begin
process 	(A)
begin
	if A (19 downto 9)= "11001001000"  then
  		CS <= '0';
		ALE <= '1';
		
	else
	   CS <= '1';
		ALE <= '0';
  end if;
end process;

	 
process (SMEMR,SMEMW)
begin	
  
  RD <= SMEMR;
  WR <= SMEMW;
end process;


RST <= '1';
DEFSUP <= '0';




process (IRQ9)
begin	
  IRQ <= IRQ9;
end process;



 end Behavioral;