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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: xccpld Date: 1-12-2008, 9:22AM
Device Used: XC9536-10-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
7 /36 ( 19%) 5 /180 ( 3%) 14 /72 ( 19%) 0 /36 ( 0%) 21 /34 ( 62%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 7/18 14/36 14 5/90 7/17
FB2 0/18 0/36 0 0/90 0/17
----- ----- ----- -----
7/36 14/72 5/180 7/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 14 14 | I/O : 20 28
Output : 7 7 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 21 21
** Power Data **
There are 7 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 7 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DEFSUP 0 0 FB1_6 2 I/O O STD FAST
RST 0 0 FB1_7 1 GCK/I/O O STD FAST
IRQ 1 1 FB1_8 3 I/O O STD FAST
ALE 1 11 FB1_9 5 I/O O STD FAST
WR 1 1 FB1_10 6 I/O O STD FAST
RD 1 1 FB1_11 7 I/O O STD FAST
CS 1 11 FB1_12 8 I/O O STD FAST
** 14 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
A<9> FB1_14 13 I/O I
A<10> FB1_15 14 I/O I
A<11> FB1_16 16 I/O I
A<12> FB1_17 18 I/O I
IRQ9 FB2_7 32 I/O I
SMEMW FB2_9 30 I/O I
SMEMR FB2_10 29 I/O I
A<19> FB2_11 28 I/O I
A<18> FB2_12 27 I/O I
A<17> FB2_13 23 I/O I
A<16> FB2_14 22 I/O I
A<15> FB2_15 21 I/O I
A<14> FB2_16 20 I/O I
A<13> FB2_17 19 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 14/22
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 40 I/O
(unused) 0 0 0 5 FB1_2 41 I/O
(unused) 0 0 0 5 FB1_3 43 GCK/I/O
(unused) 0 0 0 5 FB1_4 42 I/O
(unused) 0 0 0 5 FB1_5 44 GCK/I/O
DEFSUP 0 0 0 5 FB1_6 2 I/O O
RST 0 0 0 5 FB1_7 1 GCK/I/O O
IRQ 1 0 0 4 FB1_8 3 I/O O
ALE 1 0 0 4 FB1_9 5 I/O O
WR 1 0 0 4 FB1_10 6 I/O O
RD 1 0 0 4 FB1_11 7 I/O O
CS 1 0 0 4 FB1_12 8 I/O O
(unused) 0 0 0 5 FB1_13 12 I/O
(unused) 0 0 0 5 FB1_14 13 I/O I
(unused) 0 0 0 5 FB1_15 14 I/O I
(unused) 0 0 0 5 FB1_16 16 I/O I
(unused) 0 0 0 5 FB1_17 18 I/O I
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: A<10> 6: A<15> 11: A<9>
2: A<11> 7: A<16> 12: IRQ9
3: A<12> 8: A<17> 13: SMEMR
4: A<13> 9: A<18> 14: SMEMW
5: A<14> 10: A<19>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DEFSUP ........................................ 0 0
RST ........................................ 0 0
IRQ ...........X............................ 1 1
ALE XXXXXXXXXXX............................. 11 11
WR .............X.......................... 1 1
RD ............X........................... 1 1
CS XXXXXXXXXXX............................. 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O
(unused) 0 0 0 5 FB2_2 38 I/O
(unused) 0 0 0 5 FB2_3 36 GTS/I/O
(unused) 0 0 0 5 FB2_4 37 I/O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O
(unused) 0 0 0 5 FB2_6 33 GSR/I/O
(unused) 0 0 0 5 FB2_7 32 I/O I
(unused) 0 0 0 5 FB2_8 31 I/O
(unused) 0 0 0 5 FB2_9 30 I/O I
(unused) 0 0 0 5 FB2_10 29 I/O I
(unused) 0 0 0 5 FB2_11 28 I/O I
(unused) 0 0 0 5 FB2_12 27 I/O I
(unused) 0 0 0 5 FB2_13 23 I/O I
(unused) 0 0 0 5 FB2_14 22 I/O I
(unused) 0 0 0 5 FB2_15 21 I/O I
(unused) 0 0 0 5 FB2_16 20 I/O I
(unused) 0 0 0 5 FB2_17 19 I/O I
(unused) 0 0 0 5 FB2_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
ALE <= (A(19) AND A(18) AND A(15) AND A(12) AND NOT A(9) AND NOT A(13) AND
NOT A(11) AND NOT A(10) AND NOT A(17) AND NOT A(16) AND NOT A(14));
CS <= NOT ((A(19) AND A(18) AND A(15) AND A(12) AND NOT A(9) AND NOT A(13) AND
NOT A(11) AND NOT A(10) AND NOT A(17) AND NOT A(16) AND NOT A(14)));
DEFSUP <= '0';
IRQ <= IRQ9;
RD <= SMEMR;
RST <= '1';
WR <= SMEMW;
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9536-10-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9536-10-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 RST 23 A<17>
2 DEFSUP 24 TDO
3 IRQ 25 GND
4 GND 26 VCC
5 ALE 27 A<18>
6 WR 28 A<19>
7 RD 29 SMEMR
8 CS 30 SMEMW
9 TDI 31 TIE
10 TMS 32 IRQ9
11 TCK 33 TIE
12 TIE 34 TIE
13 A<9> 35 VCC
14 A<10> 36 TIE
15 VCC 37 TIE
16 A<11> 38 TIE
17 GND 39 TIE
18 A<12> 40 TIE
19 A<13> 41 TIE
20 A<14> 42 TIE
21 A<15> 43 TIE
22 A<16> 44 TIE
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9536-10-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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