bs.vhd

是基于EDA系统上的一24小时制的数字钟设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
entity bs is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
     clk:in std_logic;
q2k,q1k:out std_logic);
end bs;
architecture bss of bs is
begin
 process(clk,m1,m0,s1,s0)
 begin
   if clk='0' then q1k<='0'; 
    elsif(m1="0101" and m0="1001" and s1="0101" ) then
    if(s0="0101" or s0="0110" or s0="0111" or s0="1000" or s0="1001") then
        q1k<='1';
      else
        q1k<='0';
      end if;
    end if;
end process;
process(clk)
begin
  if m1="0000"and m0="0000" and s1="0000"and s0="0000"and clk='1' then
      q2k<='1';
    else
     q2k<='0';
  end if;
 end process;
 end bss;