ledscan.vhd

来自「VHDL设计实例 VHDL设计实例」· VHDL 代码 · 共 24 行

--ledscan.vhd 4 digit bcd-to-7 segment scan display
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.components.all;
entity ledscan is
port(
  clk : in std_logic;--synchronous
  f1k_ena : in std_logic;--scan clock
  bcd_data : in std_logic_vector(15 downto 0);--input bcd
  ledseg : out std_logic_vector(6 downto 0);--output to 7 segment 
  ledcom : out std_logic_vector(3 downto 0));--7 segment enable
end ledscan;
architecture behavior of ledscan is 
  signal com_clk : std_logic_vector(1 downto 0);
  signal bcd_led : std_logic_vector(3 downto 0);
begin 
  u0: comcoun port map (clk,f1k_ena,com_clk);-- 7 segment com scan counter
  u1: com_encode port map (com_clk,ledcom);--7 segment com encode
  u2: bcd_mux port map (com_clk,bcd_data,bcd_led);--multiplexer
  u3: bcd_7seg port map (bcd_led,ledseg);--bcd to 7 segment encoder
end behavior;