sdrm.ll

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

Revision 3
; Created by bitgen D.24 at Thu Nov  2 14:18:21 2000
; Bit lines have the following form:
; <offset> <frame number> <frame offset> <information>
; <information> may be zero or more <kw>=<value> pairs
; Block=<blockname     specifies the block associated with this
;                      memory cell.
;
; Latch=<name>         specifies the latch associated with this memory cell.
;
; Net=<netname>        specifies the user net associated with this
;                      memory cell.
;
; COMPARE=[YES | NO]   specifies whether or not it is appropriate
;                      to compare this bit position between a
;                      "program" and a "readback" bitstream.
;                      If not present the default is NO.
;
; Ram=<ram id>:<bit>   This is used in cases where a CLB function
; Rom=<ram id>:<bit>   generator is used as RAM (or ROM).  <Ram id>
;                      will be either 'F', 'G', or 'M', indicating
;                      that it is part of a single F or G function
;                      generator used as RAM, or as a single RAM
;                      (or ROM) built from both F and G.  <Bit> is
;                      a decimal number.
;
; Info lines have the following form:
; Info <name>=<value>  specifies a bit associated with the LCA
;                      configuration options, and the value of
;                      that bit.  The names of these bits may have
;                      special meaning to software reading the .ll file.
;
Info STARTSEL0=1
Bit     6280     11    161 Block=CLB_R25C25.S1 Latch=XQ Net=ref_max(11)
Bit     6298     11    179 Block=CLB_R24C25.S1 Latch=XQ Net=ref_max(5)
Bit     6406     11    287 Block=CLB_R18C25.S1 Latch=XQ Net=sys_int_int/data_reg(15)
Bit     9880     17     89 Block=CLB_R29C25.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(10)
Bit     9898     17    107 Block=CLB_R28C25.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(4)
Bit     9916     17    125 Block=CLB_R27C25.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(14)
Bit     9952     17    161 Block=CLB_R25C25.S1 Latch=YQ Net=ref_max(10)
Bit     9970     17    179 Block=CLB_R24C25.S1 Latch=YQ Net=ref_max(4)
Bit    10078     17    287 Block=CLB_R18C25.S1 Latch=YQ Net=sys_int_int/data_reg(14)
Bit    24747     41    268 Block=CLB_R19C25.S0 Ram=G:15
Bit    25359     42    268 Block=CLB_R19C25.S0 Ram=G:14
Bit    25971     43    268 Block=CLB_R19C25.S0 Ram=G:13
Bit    26583     44    268 Block=CLB_R19C25.S0 Ram=G:12
Bit    27195     45    268 Block=CLB_R19C25.S0 Ram=G:11
Bit    27807     46    268 Block=CLB_R19C25.S0 Ram=G:10
Bit    28419     47    268 Block=CLB_R19C25.S0 Ram=G:9
Bit    29031     48    268 Block=CLB_R19C25.S0 Ram=G:8
Bit    29643     49    268 Block=CLB_R19C25.S0 Ram=G:7
Bit    30255     50    268 Block=CLB_R19C25.S0 Ram=G:6
Bit    30867     51    268 Block=CLB_R19C25.S0 Ram=G:5
Bit    31479     52    268 Block=CLB_R19C25.S0 Ram=G:4
Bit    32091     53    268 Block=CLB_R19C25.S0 Ram=G:3
Bit    32703     54    268 Block=CLB_R19C25.S0 Ram=G:2
Bit    33315     55    268 Block=CLB_R19C25.S0 Ram=G:1
Bit    33927     56    268 Block=CLB_R19C25.S0 Ram=G:0
Bit    35638     59    143 Block=CLB_R26C24.S1 Latch=XQ Net=ref_max(13)
Bit    35674     59    179 Block=CLB_R24C24.S1 Latch=XQ Net=sd_add_op(9)
Bit    35692     59    197 Block=CLB_R23C24.S1 Latch=XQ Net=sys_int_int/data_reg(21)
Bit    35710     59    215 Block=CLB_R22C24.S1 Latch=XQ Net=add_reg(21)
Bit    35764     59    269 Block=CLB_R19C24.S1 Latch=XQ Net=ki_max(1)
Bit    35782     59    287 Block=CLB_R18C24.S1 Latch=XQ Net=add_reg(15)
Bit    39220     65     53 Block=CLB_R31C24.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(0)
Bit    39238     65     71 Block=CLB_R30C24.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(1)
Bit    39256     65     89 Block=CLB_R29C24.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(2)
Bit    39274     65    107 Block=CLB_R28C24.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(15)
Bit    39310     65    143 Block=CLB_R26C24.S1 Latch=YQ Net=ref_max(12)
Bit    39346     65    179 Block=CLB_R24C24.S1 Latch=YQ Net=sd_add_op(8)
Bit    39364     65    197 Block=CLB_R23C24.S1 Latch=YQ Net=sys_int_int/data_reg(20)
Bit    39382     65    215 Block=CLB_R22C24.S1 Latch=YQ Net=add_reg(20)
Bit    39436     65    269 Block=CLB_R19C24.S1 Latch=YQ Net=ki_max(0)
Bit    39454     65    287 Block=CLB_R18C24.S1 Latch=YQ Net=add_reg(14)
Bit    58264     96    125 Block=CLB_R27C24.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(12)
Bit    58282     96    143 Block=CLB_R26C24.S0 Latch=YQ Net=ref_max(2)
Bit    58300     96    161 Block=CLB_R25C24.S0 Latch=YQ Net=ref_max(0)
Bit    58354     96    215 Block=CLB_R22C24.S0 Latch=YQ Net=sd_add_op(10)
Bit    58426     96    287 Block=CLB_R18C24.S0 Latch=YQ Net=sd_add_op(4)
Bit    61954    102    143 Block=CLB_R26C24.S0 Latch=XQ Net=ref_max(3)
Bit    61972    102    161 Block=CLB_R25C24.S0 Latch=XQ Net=ref_max(1)
Bit    62098    102    287 Block=CLB_R18C24.S0 Latch=XQ Net=sd_add_op(5)
Bit    63915    105    268 Block=CLB_R19C26.S1 Ram=G:0
Bit    63969    105    322 Block=CLB_R16C26.S1 Ram=G:0
Bit    64527    106    268 Block=CLB_R19C26.S1 Ram=G:1
Bit    64581    106    322 Block=CLB_R16C26.S1 Ram=G:1
Bit    65139    107    268 Block=CLB_R19C26.S1 Ram=G:2
Bit    65193    107    322 Block=CLB_R16C26.S1 Ram=G:2
Bit    65751    108    268 Block=CLB_R19C26.S1 Ram=G:3
Bit    65805    108    322 Block=CLB_R16C26.S1 Ram=G:3
Bit    66363    109    268 Block=CLB_R19C26.S1 Ram=G:4
Bit    66417    109    322 Block=CLB_R16C26.S1 Ram=G:4
Bit    66975    110    268 Block=CLB_R19C26.S1 Ram=G:5
Bit    67029    110    322 Block=CLB_R16C26.S1 Ram=G:5
Bit    67587    111    268 Block=CLB_R19C26.S1 Ram=G:6
Bit    67641    111    322 Block=CLB_R16C26.S1 Ram=G:6
Bit    68199    112    268 Block=CLB_R19C26.S1 Ram=G:7
Bit    68253    112    322 Block=CLB_R16C26.S1 Ram=G:7
Bit    68704    113    161 Block=CLB_R25C26.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(11)
Bit    68811    113    268 Block=CLB_R19C26.S1 Ram=G:8
Bit    68865    113    322 Block=CLB_R16C26.S1 Ram=G:8
Bit    69423    114    268 Block=CLB_R19C26.S1 Ram=G:9
Bit    69477    114    322 Block=CLB_R16C26.S1 Ram=G:9
Bit    70035    115    268 Block=CLB_R19C26.S1 Ram=G:10
Bit    70089    115    322 Block=CLB_R16C26.S1 Ram=G:10
Bit    70647    116    268 Block=CLB_R19C26.S1 Ram=G:11
Bit    70701    116    322 Block=CLB_R16C26.S1 Ram=G:11
Bit    71259    117    268 Block=CLB_R19C26.S1 Ram=G:12
Bit    71313    117    322 Block=CLB_R16C26.S1 Ram=G:12
Bit    71871    118    268 Block=CLB_R19C26.S1 Ram=G:13
Bit    71925    118    322 Block=CLB_R16C26.S1 Ram=G:13
Bit    72483    119    268 Block=CLB_R19C26.S1 Ram=G:14
Bit    72537    119    322 Block=CLB_R16C26.S1 Ram=G:14
Bit    73095    120    268 Block=CLB_R19C26.S1 Ram=G:15
Bit    73149    120    322 Block=CLB_R16C26.S1 Ram=G:15
Bit    83391    137    160 Block=CLB_R25C26.S0 Ram=G:15
Bit    84003    138    160 Block=CLB_R25C26.S0 Ram=G:14
Bit    84615    139    160 Block=CLB_R25C26.S0 Ram=G:13
Bit    85227    140    160 Block=CLB_R25C26.S0 Ram=G:12
Bit    85839    141    160 Block=CLB_R25C26.S0 Ram=G:11
Bit    86451    142    160 Block=CLB_R25C26.S0 Ram=G:10
Bit    87063    143    160 Block=CLB_R25C26.S0 Ram=G:9
Bit    87586    144     71 Block=CLB_R30C26.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(5)
Bit    87604    144     89 Block=CLB_R29C26.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(7)
Bit    87658    144    143 Block=CLB_R26C26.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(13)
Bit    87675    144    160 Block=CLB_R25C26.S0 Ram=G:8
Bit    87694    144    179 Block=CLB_R24C26.S0 Latch=YQ Net=ref_max(6)
Bit    87838    144    323 Block=CLB_R16C26.S0 Latch=YQ Net=sys_int_int/data_reg(30)
Bit    88287    145    160 Block=CLB_R25C26.S0 Ram=G:7
Bit    88899    146    160 Block=CLB_R25C26.S0 Ram=G:6
Bit    89511    147    160 Block=CLB_R25C26.S0 Ram=G:5
Bit    90123    148    160 Block=CLB_R25C26.S0 Ram=G:4
Bit    90735    149    160 Block=CLB_R25C26.S0 Ram=G:3
Bit    91347    150    160 Block=CLB_R25C26.S0 Ram=G:2
Bit    91366    150    179 Block=CLB_R24C26.S0 Latch=XQ Net=ref_max(7)
Bit    91510    150    323 Block=CLB_R16C26.S0 Latch=XQ Net=sys_int_int/data_reg(31)
Bit    91959    151    160 Block=CLB_R25C26.S0 Ram=G:1
Bit    92571    152    160 Block=CLB_R25C26.S0 Ram=G:0
Bit    94390    155    143 Block=CLB_R26C23.S1 Latch=XQ Net=sys_int_int/data_reg(17)
Bit    94516    155    269 Block=CLB_R19C23.S1 Latch=XQ Net=sys_int_int/data_reg(7)
Bit    94552    155    305 Block=CLB_R17C23.S1 Latch=XQ Net=sys_int_int/data_reg(11)
Bit    94588    155    341 Block=CLB_R15C23.S1 Latch=XQ Net=sd_add_op(1)
Bit    94606    155    359 Block=CLB_R14C23.S1 Latch=XQ Net=ad_reg(11)
Bit    98062    161    143 Block=CLB_R26C23.S1 Latch=YQ Net=sys_int_int/data_reg(16)
Bit    98098    161    179 Block=CLB_R24C23.S1 Latch=YQ Net=sdrm_t_int/auto_ref_out
Bit    98188    161    269 Block=CLB_R19C23.S1 Latch=YQ Net=sys_int_int/data_reg(6)
Bit    98224    161    305 Block=CLB_R17C23.S1 Latch=YQ Net=sys_int_int/data_reg(10)
Bit    98260    161    341 Block=CLB_R15C23.S1 Latch=YQ Net=sd_add_op(0)
Bit    98278    161    359 Block=CLB_R14C23.S1 Latch=YQ Net=ad_reg(10)
Bit   116998    192    107 Block=CLB_R28C23.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(3)
Bit   117034    192    143 Block=CLB_R26C23.S0 Latch=YQ Net=ref_max(14)
Bit   117142    192    251 Block=CLB_R20C23.S0 Latch=YQ Net=sys_int_int/data_reg(8)
Bit   117160    192    269 Block=CLB_R19C23.S0 Latch=YQ Net=ki_max(2)
Bit   117178    192    287 Block=CLB_R18C23.S0 Latch=YQ Net=add_reg(6)
Bit   117196    192    305 Block=CLB_R17C23.S0 Latch=YQ Net=sd_ras_op
Bit   117232    192    341 Block=CLB_R15C23.S0 Latch=YQ Net=add_reg(10)
Bit   117268    192    377 Block=CLB_R13C23.S0 Latch=YQ Net=ad_o(6)
Bit   120706    198    143 Block=CLB_R26C23.S0 Latch=XQ Net=ref_max(15)
Bit   120814    198    251 Block=CLB_R20C23.S0 Latch=XQ Net=sys_int_int/data_reg(9)
Bit   120832    198    269 Block=CLB_R19C23.S0 Latch=XQ Net=ki_max(3)
Bit   120850    198    287 Block=CLB_R18C23.S0 Latch=XQ Net=add_reg(7)
Bit   120868    198    305 Block=CLB_R17C23.S0 Latch=XQ Net=sd_we_op
Bit   120904    198    341 Block=CLB_R15C23.S0 Latch=XQ Net=add_reg(11)
Bit   120940    198    377 Block=CLB_R13C23.S0 Latch=XQ Net=ad_o(7)
Bit   122721    201    322 Block=CLB_R16C27.S1 Ram=G:0
Bit   122739    201    340 Block=CLB_R15C27.S1 Ram=G:0
Bit   123333    202    322 Block=CLB_R16C27.S1 Ram=G:1
Bit   123351    202    340 Block=CLB_R15C27.S1 Ram=G:1
Bit   123945    203    322 Block=CLB_R16C27.S1 Ram=G:2
Bit   123963    203    340 Block=CLB_R15C27.S1 Ram=G:2
Bit   124557    204    322 Block=CLB_R16C27.S1 Ram=G:3
Bit   124575    204    340 Block=CLB_R15C27.S1 Ram=G:3
Bit   125169    205    322 Block=CLB_R16C27.S1 Ram=G:4
Bit   125187    205    340 Block=CLB_R15C27.S1 Ram=G:4
Bit   125781    206    322 Block=CLB_R16C27.S1 Ram=G:5
Bit   125799    206    340 Block=CLB_R15C27.S1 Ram=G:5
Bit   126393    207    322 Block=CLB_R16C27.S1 Ram=G:6
Bit   126411    207    340 Block=CLB_R15C27.S1 Ram=G:6
Bit   127005    208    322 Block=CLB_R16C27.S1 Ram=G:7
Bit   127023    208    340 Block=CLB_R15C27.S1 Ram=G:7
Bit   127366    209     71 Block=CLB_R30C27.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(9)
Bit   127402    209    107 Block=CLB_R28C27.S1 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(6)
Bit   127617    209    322 Block=CLB_R16C27.S1 Ram=G:8
Bit   127635    209    340 Block=CLB_R15C27.S1 Ram=G:8
Bit   128229    210    322 Block=CLB_R16C27.S1 Ram=G:9
Bit   128247    210    340 Block=CLB_R15C27.S1 Ram=G:9
Bit   128841    211    322 Block=CLB_R16C27.S1 Ram=G:10
Bit   128859    211    340 Block=CLB_R15C27.S1 Ram=G:10
Bit   129453    212    322 Block=CLB_R16C27.S1 Ram=G:11
Bit   129471    212    340 Block=CLB_R15C27.S1 Ram=G:11
Bit   130065    213    322 Block=CLB_R16C27.S1 Ram=G:12
Bit   130083    213    340 Block=CLB_R15C27.S1 Ram=G:12
Bit   130677    214    322 Block=CLB_R16C27.S1 Ram=G:13
Bit   130695    214    340 Block=CLB_R15C27.S1 Ram=G:13
Bit   131289    215    322 Block=CLB_R16C27.S1 Ram=G:14
Bit   131307    215    340 Block=CLB_R15C27.S1 Ram=G:14
Bit   131901    216    322 Block=CLB_R16C27.S1 Ram=G:15
Bit   131919    216    340 Block=CLB_R15C27.S1 Ram=G:15
Bit   142377    233    394 Block=CLB_R12C27.S0 Ram=G:15
Bit   142989    234    394 Block=CLB_R12C27.S0 Ram=G:14
Bit   143601    235    394 Block=CLB_R12C27.S0 Ram=G:13
Bit   144213    236    394 Block=CLB_R12C27.S0 Ram=G:12
Bit   144825    237    394 Block=CLB_R12C27.S0 Ram=G:11
Bit   145437    238    394 Block=CLB_R12C27.S0 Ram=G:10
Bit   146049    239    394 Block=CLB_R12C27.S0 Ram=G:9
Bit   146374    240    107 Block=CLB_R28C27.S0 Latch=YQ Net=sdrm_t_int/ref_cntr_inst/rcount(8)
Bit   146428    240    161 Block=CLB_R25C27.S0 Latch=YQ Net=ref_max(8)
Bit   146500    240    233 Block=CLB_R21C27.S0 Latch=YQ Net=ad_o(0)
Bit   146661    240    394 Block=CLB_R12C27.S0 Ram=G:8
Bit   147273    241    394 Block=CLB_R12C27.S0 Ram=G:7
Bit   147885    242    394 Block=CLB_R12C27.S0 Ram=G:6
Bit   148497    243    394 Block=CLB_R12C27.S0 Ram=G:5
Bit   149109    244    394 Block=CLB_R12C27.S0 Ram=G:4
Bit   149721    245    394 Block=CLB_R12C27.S0 Ram=G:3
Bit   150100    246    161 Block=CLB_R25C27.S0 Latch=XQ Net=ref_max(9)
Bit   150172    246    233 Block=CLB_R21C27.S0 Latch=XQ Net=ad_o(1)
Bit   150333    246    394 Block=CLB_R12C27.S0 Ram=G:2
Bit   150945    247    394 Block=CLB_R12C27.S0 Ram=G:1
Bit   151557    248    394 Block=CLB_R12C27.S0 Ram=G:0
Bit   153214    251    215 Block=CLB_R22C22.S1 Latch=XQ Net=add_reg(17)
Bit   153304    251    305 Block=CLB_R17C22.S1 Latch=XQ Net=sd_cas_op
Bit   153322    251    323 Block=CLB_R16C22.S1 Latch=XQ Net=add_reg(13)
Bit   153340    251    341 Block=CLB_R15C22.S1 Latch=XQ Net=add_reg(3)
Bit   156886    257    215 Block=CLB_R22C22.S1 Latch=YQ Net=add_reg(16)
Bit   156976    257    305 Block=CLB_R17C22.S1 Latch=YQ Net=sdrm_t_int/clr_ref_d
Bit   156994    257    323 Block=CLB_R16C22.S1 Latch=YQ Net=add_reg(12)
Bit   157012    257    341 Block=CLB_R15C22.S1 Latch=YQ Net=add_reg(2)
Bit   171771    281    412 Block=CLB_R11C22.S0 Ram=G:15
Bit   172383    282    412 Block=CLB_R11C22.S0 Ram=G:14
Bit   172995    283    412 Block=CLB_R11C22.S0 Ram=G:13
Bit   173607    284    412 Block=CLB_R11C22.S0 Ram=G:12
Bit   174219    285    412 Block=CLB_R11C22.S0 Ram=G:11
Bit   174831    286    412 Block=CLB_R11C22.S0 Ram=G:10
Bit   175443    287    412 Block=CLB_R11C22.S0 Ram=G:9
Bit   175840    288    197 Block=CLB_R23C22.S0 Latch=YQ Net=sys_int_int/data_reg(18)
Bit   175876    288    233 Block=CLB_R21C22.S0 Latch=YQ Net=sd_add_op(6)
Bit   175894    288    251 Block=CLB_R20C22.S0 Latch=YQ Net=add_reg(8)
Bit   175912    288    269 Block=CLB_R19C22.S0 Latch=YQ Net=sdrm_t_int/ki_cntr_inst/count_sig(1)
Bit   175930    288    287 Block=CLB_R18C22.S0 Latch=YQ Net=sdrm_t_int/ki_cntr_inst/count_sig(3)
Bit   175948    288    305 Block=CLB_R17C22.S0 Latch=YQ Net=sys_int_int/data_reg(12)
Bit   175966    288    323 Block=CLB_R16C22.S0 Latch=YQ Net=sd_add_op(2)
Bit   176055    288    412 Block=CLB_R11C22.S0 Ram=G:8