sdrm.ucf

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

NET Locked_i MAXDELAY = 6.5ns;

#####################
# clock constraints #
#####################
NET "Clkp"     PERIOD = 16ns ;

#
#specifying clock periods between clk1x and clk2x
#
NET Clk_i  TNM=c2x;
NET Clk_j  TNM=c1x;
TIMESPEC TS10= FROM: c2x: TO: c1x: 8ns;
TIMESPEC TS11= FROM: c1x: TO: c2x: 8ns;

################################
# input and output constraints #
################################
#
#The min setup (Tsu) of the SDRAM-8 is 2ns, plus 500ps of board delay
#we need to add this OFFSET to all outputs to SDRAM
#
NET sd_add(*) OFFSET = OUT : 2.5 : BEFORE : Clkp ;
NET sd_data(*) OFFSET = OUT : 2.5 : BEFORE : Clkp ;
NET sd_ras OFFSET = OUT	: 2.5 : BEFORE : Clkp ;
NET sd_cas OFFSET = OUT	: 2.5 : BEFORE : Clkp ;
NET sd_we OFFSET = OUT : 2.5 : BEFORE : Clkp ;
NET sd_ba OFFSET = OUT : 2.5 : BEFORE : Clkp ;
#
#The max clock-to-out (Tac) of the SDRAM-8 is 6ns, plus 300ps of board delay
#we need to add this OFFSET to all inputs from SDRAM
#
NET sd_data(*) OFFSET = IN : 6.3 : AFTER : Clkp;


###########################################
# set NODELAY attribute for input signals #
##########################################
#By default, the IBUF has a DELAY element to guarantee 0 hold time
#By turning off the DELAY element, we save ~500ps in IBUF delay
NET sd_data(0) NODELAY;
NET sd_data(1) NODELAY;
NET sd_data(2) NODELAY;
NET sd_data(3) NODELAY;
NET sd_data(4) NODELAY;
NET sd_data(5) NODELAY;
NET sd_data(6) NODELAY;
NET sd_data(7) NODELAY;
NET sd_data(8) NODELAY;
NET sd_data(9) NODELAY;
NET sd_data(10) NODELAY;
NET sd_data(11) NODELAY;
NET sd_data(12) NODELAY;
NET sd_data(13) NODELAY;
NET sd_data(14) NODELAY;
NET sd_data(15) NODELAY;
NET sd_data(16) NODELAY;
NET sd_data(17) NODELAY;
NET sd_data(18) NODELAY;
NET sd_data(19) NODELAY;
NET sd_data(20) NODELAY;
NET sd_data(21) NODELAY;
NET sd_data(22) NODELAY;
NET sd_data(23) NODELAY;
NET sd_data(24) NODELAY;
NET sd_data(25) NODELAY;
NET sd_data(26) NODELAY;
NET sd_data(27) NODELAY;
NET sd_data(28) NODELAY;
NET sd_data(29) NODELAY;
NET sd_data(30) NODELAY;
NET sd_data(31) NODELAY;
NET AD(0) NODELAY;
NET AD(1) NODELAY;
NET AD(2) NODELAY;
NET AD(3) NODELAY;
NET AD(4) NODELAY;
NET AD(5) NODELAY;
NET AD(6) NODELAY;
NET AD(7) NODELAY;
NET AD(8) NODELAY;
NET AD(9) NODELAY;
NET AD(10) NODELAY;
NET AD(11) NODELAY;
NET AD(12) NODELAY;
NET AD(13) NODELAY;
NET AD(14) NODELAY;
NET AD(15) NODELAY;
NET AD(16) NODELAY;
NET AD(17) NODELAY;
NET AD(18) NODELAY;
NET AD(19) NODELAY;
NET AD(20) NODELAY;
NET AD(21) NODELAY;
NET AD(22) NODELAY;
NET AD(23) NODELAY;
NET AD(24) NODELAY;
NET AD(25) NODELAY;
NET AD(26) NODELAY;
NET AD(27) NODELAY;
NET AD(28) NODELAY;
NET AD(29) NODELAY;
NET AD(30) NODELAY;
NET AD(31) NODELAY;

##################################
# Locking down IOs for the board #
##################################

#signals interfacing to SDRAM
NET sd_add(0) LOC = E1;
NET sd_add(1) LOC = E2;
NET sd_add(2) LOC = E3;
NET sd_add(3) LOC = D1;
NET sd_add(4) LOC = E4;
NET sd_add(5) LOC = AF2; 
NET sd_add(6) LOC = AD3;
NET sd_add(7) LOC = AE2; 
NET sd_add(8) LOC = AD2;
NET sd_add(9) LOC = AC3;
NET sd_add(10) LOC = AD1;

NET sd_cke LOC = AC2;
NET sd_ba LOC = F3;
NET sd_cs1 LOC = F2; 
NET sd_cs2 LOC = AJ6; 
NET sd_ras LOC = G2; 
NET sd_cas LOC = H3; 
NET sd_we LOC = H2; 
NET sd_dqm(0) LOC = H1; 
NET sd_dqm(1) LOC = AF3; 
NET sd_dqm(2) LOC = AG2; 
NET sd_dqm(3) LOC = AG1; 

NET sd_data(0) LOC = M3; 
NET sd_data(1) LOC = M4; 
NET sd_data(2) LOC = L2; 
NET sd_data(3) LOC = L3;
NET sd_data(4) LOC = K1; 
NET sd_data(5) LOC = J2; 
NET sd_data(6) LOC = J3; 
NET sd_data(7) LOC = J4; 
NET sd_data(8) LOC = R4;
NET sd_data(9) LOC = R3;
NET sd_data(10) LOC = P2; 
NET sd_data(11) LOC = P3; 
NET sd_data(12) LOC = N1; 
NET sd_data(13) LOC = N3; 
NET sd_data(14) LOC = M1; 
NET sd_data(15) LOC = M2;
NET sd_data(16) LOC = AB4;
NET sd_data(17) LOC = AA3; 
NET sd_data(18) LOC = AA2; 
NET sd_data(19) LOC = Y2; 
NET sd_data(20) LOC = Y4; 
NET sd_data(21) LOC = Y3; 
NET sd_data(22) LOC = Y1; 
NET sd_data(23) LOC = W1; 
NET sd_data(24) LOC = W3; 
NET sd_data(25) LOC = V2; 
NET sd_data(26) LOC = V3; 
NET sd_data(27) LOC = U1; 
NET sd_data(28) LOC = U2;
NET sd_data(29) LOC = U3;
NET sd_data(30) LOC = R1;
NET sd_data(31) LOC = R2;  

#Clock signals
NET Clkp LOC = AL16;
NET Clk_FBp LOC = AK16;
NET Clk_SDp LOC = AL17;

#signals interfacing to processor
NET Reset LOC = AJ4;
NET we_rn LOC = U29;
NET data_addr_n LOC = U30;

NET AD(0) LOC = W30;  
NET AD(1) LOC = W29;  
NET AD(2) LOC = Y31;  
NET AD(3) LOC = Y30;  
NET AD(4) LOC = Y29;  
NET AD(5) LOC = Y28;  
NET AD(6) LOC = AA30;  
NET AD(7) LOC = AB31;  
NET AD(8) LOC = J30;  
NET AD(9) LOC = K30; 
NET AD(10) LOC = K31;  
NET AD(11) LOC = L29;  
NET AD(12) LOC = L30;  
NET AD(13) LOC = M30;  
NET AD(14) LOC = M29;  
NET AD(15) LOC = M31;  
NET AD(16) LOC = AB29;  
NET AD(17) LOC = AC30;  
NET AD(18) LOC = AC29;  
NET AD(19) LOC = AC28; 
NET AD(20) LOC = AD31;  
NET AD(21) LOC = AD30;  
NET AD(22) LOC = AD28;  
NET AD(23) LOC = AE30;
NET AD(24) LOC = N31;  
NET AD(25) LOC = N30;  
NET AD(26) LOC = P30; 
NET AD(27) LOC = P29;  
NET AD(28) LOC = R31;  
NET AD(29) LOC = R30;  
NET AD(30) LOC = R29;  
NET AD(31) LOC = T31;