time_sim.vhd

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

  signal SD_DATA_O_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_11_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_25_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_25_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_25_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_17_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_17_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_17_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_21_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_21_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_21_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_13_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_27_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_27_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_27_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_19_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_19_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_19_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_31_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_31_GROM : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_31_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_23_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_23_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_23_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_15_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_29_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_29_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_29_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_25_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_25_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_25_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_17_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_17_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_17_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_27_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_27_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_27_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_19_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_19_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_19_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_29_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_29_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_29_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_5_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_5_GSHIFT : STD_LOGIC; 
  signal SD_BA_OP_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_14_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_14_0_AND2_FROM : STD_LOGIC; 
  signal SD_DATA_R_11_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_21_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_21_FROM : STD_LOGIC; 
  signal SD_DATA_R_21_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_21_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_13_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_31_GROM : STD_LOGIC; 
  signal SD_DATA_R_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_31_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_23_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_23_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_23_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_15_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_25_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_25_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_25_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_17_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_17_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_17_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_27_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_27_GROM : STD_LOGIC; 
  signal SD_DATA_R_27_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_27_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_19_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_19_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_19_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_29_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_29_GROM : STD_LOGIC; 
  signal SD_DATA_R_29_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_29_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_2_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_2_0_AND2_FROM : STD_LOGIC; 
  signal SD_DATA_REG_25_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_25_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_25_FROM : STD_LOGIC; 
  signal SD_DATA_REG_17_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_17_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_17_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_10_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_10_0_AND2_FROM : STD_LOGIC; 
  signal SD_DATA_T_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DOE_N_3_SRNOT : STD_LOGIC; 
  signal SD_DOE_N_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_11_CENOT : STD_LOGIC; 
  signal ADD_REG_11_SRNOT : STD_LOGIC; 
  signal ADD_REG_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_21_CENOT : STD_LOGIC; 
  signal ADD_REG_21_SRNOT : STD_LOGIC; 
  signal ADD_REG_21_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_21_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_13_CENOT : STD_LOGIC; 
  signal ADD_REG_13_SRNOT : STD_LOGIC; 
  signal ADD_REG_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_15_CENOT : STD_LOGIC; 
  signal ADD_REG_15_SRNOT : STD_LOGIC; 
  signal ADD_REG_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_17_CENOT : STD_LOGIC; 
  signal ADD_REG_17_SRNOT : STD_LOGIC; 
  signal ADD_REG_17_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_17_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_19_CENOT : STD_LOGIC; 
  signal ADD_REG_19_SRNOT : STD_LOGIC; 
  signal ADD_REG_19_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_19_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_BA_O_SRNOT : STD_LOGIC; 
  signal SD_BA_O_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_LCRY_GROM : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_LCRY_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_0_AND2_FROM : STD_LOGIC; 
  signal SD_DATA_REG_6_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_6_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_6_FROM : STD_LOGIC; 
  signal SD_DATA_REG_10_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_10_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_10_FROM : STD_LOGIC; 
  signal SD_DATA_REG_26_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_26_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_26_FROM : STD_LOGIC; 
  signal SD_DATA_REG_18_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_18_GSHIFT : STD_LOGIC; 
  signal AD_O_11_SRNOT : STD_LOGIC; 
  signal AD_O_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_21_SRNOT : STD_LOGIC; 
  signal AD_O_21_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_21_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_13_SRNOT : STD_LOGIC; 
  signal AD_O_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_31_SRNOT : STD_LOGIC; 
  signal AD_O_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_31_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_23_SRNOT : STD_LOGIC; 
  signal AD_O_23_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_23_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_15_SRNOT : STD_LOGIC; 
  signal AD_O_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_25_SRNOT : STD_LOGIC; 
  signal AD_O_25_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_25_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_17_SRNOT : STD_LOGIC; 
  signal AD_O_17_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_17_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_27_SRNOT : STD_LOGIC; 
  signal AD_O_27_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_27_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_19_SRNOT : STD_LOGIC; 
  signal AD_O_19_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_19_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_29_SRNOT : STD_LOGIC; 
  signal AD_O_29_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_29_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_TRI_LOGIC_ONE : STD_LOGIC; 
  signal AD_TRI_GSHIFT : STD_LOGIC; 
  signal AD_TRI_FROM : STD_LOGIC; 
  signal CAS_LAT_MAX_1_SRNOT : STD_LOGIC; 
  signal CAS_LAT_MAX_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal CAS_LAT_MAX_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP10_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP10_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal RCD_C_MAX_1_SRNOT : STD_LOGIC; 
  signal RCD_C_MAX_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal RCD_C_MAX_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal BURST_MAX_1_SRNOT : STD_LOGIC; 
  signal BURST_MAX_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal BURST_MAX_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal BURST_MAX_2_SRNOT : STD_LOGIC; 
  signal BURST_MAX_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_1_SRNOT : STD_LOGIC; 
  signal REF_MAX_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP11_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP11_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP20_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP20_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP12_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP12_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_7_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_7_GSHIFT : STD_LOGIC; 
  signal SD_WE_O_SRNOT : STD_LOGIC; 
  signal SD_WE_O_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP21_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP21_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP13_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP13_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_15_0_AND2_GROM : STD_LOGIC; 
  signal SD_ADD_O_10_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_10_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP30_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP30_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP22_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP22_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP14_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP14_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_11_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_11_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_11_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_4_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_4_0_AND2_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP23_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP23_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP15_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP15_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_27_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_27_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_19_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_19_GSHIFT : STD_LOGIC; 
  signal SD_DATA_T_REP24_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP24_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP16_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP16_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP25_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP25_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP17_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP17_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_LOCKED_J_LOGIC_ONE : STD_LOGIC; 
  signal SDRM_T_INT_LOCKED_J_GSHIFT : STD_LOGIC; 
  signal SDRM_T_INT_LOCKED_J_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP26_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP26_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP18_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP18_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_PRE_LOCKED_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_30_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_31_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_32_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_33_GROM : STD_LOGIC; 
  signal SD_DATA_T_REP27_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP27_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP19_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP19_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_0_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_0_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_0_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP28_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP28_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_8_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_8_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_8_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP29_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP29_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_20_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_20_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_12_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_12_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_28_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_28_GSHIFT : STD_LOGIC; 
  signal SDRM_T_INT_AUTO_REF_OUT_LOGIC_ONE : STD_LOGIC; 
  signal SDRM_T_INT_AUTO_REF_OUT_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_AUTO_R