time_sim.vhd

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_12_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_12_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_13_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_13_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_14_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_14_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_14_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_15_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_15_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_0_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_0_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_1_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_1_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_2_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_2_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_3_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_3_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_4_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_4_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_4_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_5_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_5_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_6_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_6_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_6_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_7_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_7_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_8_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_8_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_8_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_9_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_9_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_1_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_N_111_I : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_N_109_I : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_2_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_N_107_I : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_PRE_SD_READY_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_9_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_PRE_SD_READY_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_PRE_SD_READY_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_4_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_8_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_4_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_4_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_5_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_7_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_5_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_8_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_6_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_8_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_8_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_7_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_5_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_7_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_9_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_3_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_9_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SD_ADD_MX_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_N_130_I_0 : STD_LOGIC; 
  signal SDRM_T_INT_SD_ADD_MX_FROM : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_2_Q : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG_FROM : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_11_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_STATE_NS_1_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_12_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_12_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_12_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_CSLT_CNTR_INST_COUNT_SIG_1_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_CSLT_CNTR_INST_COUNT_SIG_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_CSLT_CNTR_INST_COUNT_SIG_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_N_153_GROM : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_N_153_FROM : STD_LOGIC; 
  signal SDRM_T_INT_SD_DOE_N_3_I_AND2_3_GROM : STD_LOGIC; 
  signal SDRM_T_INT_SD_DOE_N_3_I_AND2_3_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP4_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP4_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_30_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_30_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_30_FROM : STD_LOGIC; 
  signal SD_DATA_REG_22_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_22_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_22_FROM : STD_LOGIC; 
  signal SD_DATA_REG_14_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_14_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_14_FROM : STD_LOGIC; 
  signal SD_DATA_T_REP5_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP5_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_CAS_O_SRNOT : STD_LOGIC; 
  signal SD_CAS_O_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP6_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP6_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP7_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP7_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP8_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP8_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_T_REP9_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_T_REP9_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_3_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_3_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_3_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_12_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_12_0_AND2_FROM : STD_LOGIC; 
  signal REF_MAX_3_SRNOT : STD_LOGIC; 
  signal REF_MAX_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_13_SRNOT : STD_LOGIC; 
  signal REF_MAX_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_5_SRNOT : STD_LOGIC; 
  signal REF_MAX_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_31_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_31_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_31_FROM : STD_LOGIC; 
  signal SD_DATA_REG_23_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_23_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_23_FROM : STD_LOGIC; 
  signal SD_DATA_REG_15_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_15_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_15_FROM : STD_LOGIC; 
  signal REF_MAX_15_SRNOT : STD_LOGIC; 
  signal REF_MAX_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_15_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_7_SRNOT : STD_LOGIC; 
  signal REF_MAX_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal KI_MAX_1_SRNOT : STD_LOGIC; 
  signal KI_MAX_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal KI_MAX_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_9_SRNOT : STD_LOGIC; 
  signal REF_MAX_9_FROM : STD_LOGIC; 
  signal REF_MAX_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_8_0_AND2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_8_0_AND2_FROM : STD_LOGIC; 
  signal KI_MAX_3_SRNOT : STD_LOGIC; 
  signal KI_MAX_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal KI_MAX_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_11_SRNOT : STD_LOGIC; 
  signal REF_MAX_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal REF_MAX_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_1_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_3_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_1_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_5_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_3_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_7_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_5_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_9_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_7_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_9_SRNOT : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SYS_INT_INT_DATA_REG_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_1_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_3_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_5_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_7_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_9_SRNOT : STD_LOGIC; 
  signal SD_DATA_R_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_R_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_3_CENOT : STD_LOGIC; 
  signal ADD_REG_3_SRNOT : STD_LOGIC; 
  signal ADD_REG_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_5_CENOT : STD_LOGIC; 
  signal ADD_REG_5_SRNOT : STD_LOGIC; 
  signal ADD_REG_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_7_CENOT : STD_LOGIC; 
  signal ADD_REG_7_SRNOT : STD_LOGIC; 
  signal ADD_REG_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_9_CENOT : STD_LOGIC; 
  signal ADD_REG_9_SRNOT : STD_LOGIC; 
  signal ADD_REG_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal ADD_REG_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_4_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_4_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_4_FROM : STD_LOGIC; 
  signal AD_O_1_SRNOT : STD_LOGIC; 
  signal AD_O_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_3_SRNOT : STD_LOGIC; 
  signal AD_O_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_5_SRNOT : STD_LOGIC; 
  signal AD_O_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_REG_24_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_24_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_16_LOGIC_ONE : STD_LOGIC; 
  signal SD_DATA_REG_16_GSHIFT : STD_LOGIC; 
  signal SD_DATA_REG_16_FROM : STD_LOGIC; 
  signal AD_O_7_SRNOT : STD_LOGIC; 
  signal AD_O_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_9_SRNOT : STD_LOGIC; 
  signal AD_O_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal AD_O_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_RAS_O_SRNOT : STD_LOGIC; 
  signal SD_RAS_O_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal DATA_ADDR_N_REG_SRNOT : STD_LOGIC; 
  signal DATA_ADDR_N_REG_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_1_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_3_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_5_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_11_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_11_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_7_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_21_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_21_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_21_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_13_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_13_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_13_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_9_SRNOT : STD_LOGIC; 
  signal SD_ADD_O_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_ADD_O_9_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_31_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_31_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_31_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_23_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_23_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_23_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_DATA_O_15_SRNOT : STD_LOGIC; 
  signal SD_DATA_O_15_FFY_ASYNC_FF_GSR_OR : STD_LOGIC;