time_sim.vhd

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

  signal AD_22_OD : STD_LOGIC; 
  signal AD_22_TORGTS : STD_LOGIC; 
  signal AD_22_ENABLE : STD_LOGIC; 
  signal AD_22_KEEPER : STD_LOGIC; 
  signal AD_22_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_DATA_4_IBUF : STD_LOGIC; 
  signal SD_DATA_4_OUTMUX : STD_LOGIC; 
  signal SD_DATA_4_ENABLE : STD_LOGIC; 
  signal SD_DATA_4_KEEPER : STD_LOGIC; 
  signal SD_DATA_4_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_31_IBUF : STD_LOGIC; 
  signal AD_31_OD : STD_LOGIC; 
  signal AD_31_TORGTS : STD_LOGIC; 
  signal AD_31_ENABLE : STD_LOGIC; 
  signal AD_31_KEEPER : STD_LOGIC; 
  signal AD_31_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_15_IBUF : STD_LOGIC; 
  signal AD_15_OD : STD_LOGIC; 
  signal AD_15_TORGTS : STD_LOGIC; 
  signal AD_15_ENABLE : STD_LOGIC; 
  signal AD_15_KEEPER : STD_LOGIC; 
  signal AD_15_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_23_IBUF : STD_LOGIC; 
  signal AD_23_OD : STD_LOGIC; 
  signal AD_23_TORGTS : STD_LOGIC; 
  signal AD_23_ENABLE : STD_LOGIC; 
  signal AD_23_KEEPER : STD_LOGIC; 
  signal AD_23_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_DATA_5_IBUF : STD_LOGIC; 
  signal SD_DATA_5_OD : STD_LOGIC; 
  signal SD_DATA_5_ENABLE : STD_LOGIC; 
  signal SD_DATA_5_KEEPER : STD_LOGIC; 
  signal SD_DATA_5_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_16_IBUF : STD_LOGIC; 
  signal AD_16_OD : STD_LOGIC; 
  signal AD_16_TORGTS : STD_LOGIC; 
  signal AD_16_ENABLE : STD_LOGIC; 
  signal AD_16_KEEPER : STD_LOGIC; 
  signal AD_16_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_24_IBUF : STD_LOGIC; 
  signal AD_24_OD : STD_LOGIC; 
  signal AD_24_TORGTS : STD_LOGIC; 
  signal AD_24_ENABLE : STD_LOGIC; 
  signal AD_24_KEEPER : STD_LOGIC; 
  signal AD_24_OUTBUF_GTS_AND : STD_LOGIC; 
  signal DATA_ADDR_N_IBUF : STD_LOGIC; 
  signal DATA_ADDR_N_KEEPER : STD_LOGIC; 
  signal SD_DATA_6_IBUF : STD_LOGIC; 
  signal SD_DATA_6_OD : STD_LOGIC; 
  signal SD_DATA_6_ENABLE : STD_LOGIC; 
  signal SD_DATA_6_KEEPER : STD_LOGIC; 
  signal SD_DATA_6_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_25_IBUF : STD_LOGIC; 
  signal AD_25_OD : STD_LOGIC; 
  signal AD_25_TORGTS : STD_LOGIC; 
  signal AD_25_ENABLE : STD_LOGIC; 
  signal AD_25_KEEPER : STD_LOGIC; 
  signal AD_25_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_17_IBUF : STD_LOGIC; 
  signal AD_17_OD : STD_LOGIC; 
  signal AD_17_TORGTS : STD_LOGIC; 
  signal AD_17_ENABLE : STD_LOGIC; 
  signal AD_17_KEEPER : STD_LOGIC; 
  signal AD_17_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_DATA_7_IBUF : STD_LOGIC; 
  signal SD_DATA_7_OD : STD_LOGIC; 
  signal SD_DATA_7_ENABLE : STD_LOGIC; 
  signal SD_DATA_7_KEEPER : STD_LOGIC; 
  signal SD_DATA_7_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_0_IBUF : STD_LOGIC; 
  signal AD_0_OD : STD_LOGIC; 
  signal AD_0_TORGTS : STD_LOGIC; 
  signal AD_0_ENABLE : STD_LOGIC; 
  signal AD_0_KEEPER : STD_LOGIC; 
  signal AD_0_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_18_IBUF : STD_LOGIC; 
  signal AD_18_OUTMUX : STD_LOGIC; 
  signal AD_18_TORGTS : STD_LOGIC; 
  signal AD_18_ENABLE : STD_LOGIC; 
  signal AD_18_KEEPER : STD_LOGIC; 
  signal AD_18_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_26_IBUF : STD_LOGIC; 
  signal AD_26_OD : STD_LOGIC; 
  signal AD_26_TORGTS : STD_LOGIC; 
  signal AD_26_ENABLE : STD_LOGIC; 
  signal AD_26_KEEPER : STD_LOGIC; 
  signal AD_26_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_DATA_8_IBUF : STD_LOGIC; 
  signal SD_DATA_8_OUTMUX : STD_LOGIC; 
  signal SD_DATA_8_ENABLE : STD_LOGIC; 
  signal SD_DATA_8_KEEPER : STD_LOGIC; 
  signal SD_DATA_8_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_1_IBUF : STD_LOGIC; 
  signal AD_1_OD : STD_LOGIC; 
  signal AD_1_TORGTS : STD_LOGIC; 
  signal AD_1_ENABLE : STD_LOGIC; 
  signal AD_1_KEEPER : STD_LOGIC; 
  signal AD_1_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_27_IBUF : STD_LOGIC; 
  signal AD_27_OD : STD_LOGIC; 
  signal AD_27_TORGTS : STD_LOGIC; 
  signal AD_27_ENABLE : STD_LOGIC; 
  signal AD_27_KEEPER : STD_LOGIC; 
  signal AD_27_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_19_IBUF : STD_LOGIC; 
  signal AD_19_OUTMUX : STD_LOGIC; 
  signal AD_19_TORGTS : STD_LOGIC; 
  signal AD_19_ENABLE : STD_LOGIC; 
  signal AD_19_KEEPER : STD_LOGIC; 
  signal AD_19_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_DATA_9_IBUF : STD_LOGIC; 
  signal SD_DATA_9_OUTMUX : STD_LOGIC; 
  signal SD_DATA_9_ENABLE : STD_LOGIC; 
  signal SD_DATA_9_KEEPER : STD_LOGIC; 
  signal SD_DATA_9_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_2_IBUF : STD_LOGIC; 
  signal AD_2_OD : STD_LOGIC; 
  signal AD_2_TORGTS : STD_LOGIC; 
  signal AD_2_ENABLE : STD_LOGIC; 
  signal AD_2_KEEPER : STD_LOGIC; 
  signal AD_2_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_28_IBUF : STD_LOGIC; 
  signal AD_28_OUTMUX : STD_LOGIC; 
  signal AD_28_TORGTS : STD_LOGIC; 
  signal AD_28_ENABLE : STD_LOGIC; 
  signal AD_28_KEEPER : STD_LOGIC; 
  signal AD_28_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_RAS_OD : STD_LOGIC; 
  signal SD_RAS_KEEPER : STD_LOGIC; 
  signal AD_3_IBUF : STD_LOGIC; 
  signal AD_3_OD : STD_LOGIC; 
  signal AD_3_TORGTS : STD_LOGIC; 
  signal AD_3_ENABLE : STD_LOGIC; 
  signal AD_3_KEEPER : STD_LOGIC; 
  signal AD_3_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_29_IBUF : STD_LOGIC; 
  signal AD_29_OUTMUX : STD_LOGIC; 
  signal AD_29_TORGTS : STD_LOGIC; 
  signal AD_29_ENABLE : STD_LOGIC; 
  signal AD_29_KEEPER : STD_LOGIC; 
  signal AD_29_OUTBUF_GTS_AND : STD_LOGIC; 
  signal RESET_IBUF : STD_LOGIC; 
  signal RESET_KEEPER : STD_LOGIC; 
  signal AD_4_IBUF : STD_LOGIC; 
  signal AD_4_OD : STD_LOGIC; 
  signal AD_4_TORGTS : STD_LOGIC; 
  signal AD_4_ENABLE : STD_LOGIC; 
  signal AD_4_KEEPER : STD_LOGIC; 
  signal AD_4_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_CAS_OD : STD_LOGIC; 
  signal SD_CAS_KEEPER : STD_LOGIC; 
  signal AD_5_IBUF : STD_LOGIC; 
  signal AD_5_OD : STD_LOGIC; 
  signal AD_5_TORGTS : STD_LOGIC; 
  signal AD_5_ENABLE : STD_LOGIC; 
  signal AD_5_KEEPER : STD_LOGIC; 
  signal AD_5_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_6_IBUF : STD_LOGIC; 
  signal AD_6_OD : STD_LOGIC; 
  signal AD_6_TORGTS : STD_LOGIC; 
  signal AD_6_ENABLE : STD_LOGIC; 
  signal AD_6_KEEPER : STD_LOGIC; 
  signal AD_6_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_7_IBUF : STD_LOGIC; 
  signal AD_7_OD : STD_LOGIC; 
  signal AD_7_TORGTS : STD_LOGIC; 
  signal AD_7_ENABLE : STD_LOGIC; 
  signal AD_7_KEEPER : STD_LOGIC; 
  signal AD_7_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SD_CKE_LOGIC_ONE : STD_LOGIC; 
  signal SD_CKE_KEEPER : STD_LOGIC; 
  signal AD_8_IBUF : STD_LOGIC; 
  signal AD_8_OD : STD_LOGIC; 
  signal AD_8_TORGTS : STD_LOGIC; 
  signal AD_8_ENABLE : STD_LOGIC; 
  signal AD_8_KEEPER : STD_LOGIC; 
  signal AD_8_OUTBUF_GTS_AND : STD_LOGIC; 
  signal AD_9_IBUF : STD_LOGIC; 
  signal AD_9_OD : STD_LOGIC; 
  signal AD_9_TORGTS : STD_LOGIC; 
  signal AD_9_ENABLE : STD_LOGIC; 
  signal AD_9_KEEPER : STD_LOGIC; 
  signal AD_9_OUTBUF_GTS_AND : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_0_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_CRY_0_O : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_0_LOGIC_ONE : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_0_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_0_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_2_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_2_GROM : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_0_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_CRY_0_O : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_0_LOGIC_ONE : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_0_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_0_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_2_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_CRY_2_O : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_2_LOGIC_ONE : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_2_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_2_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_1_LOGIC_ZERO : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_1_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_0_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_1_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_18_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_17_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_2_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_2_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_2_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_20_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_19_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_2_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_4_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_4_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_4_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_22_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_21_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_4_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_6_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_6_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_6_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_24_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_23_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_6_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_8_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_8_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_8_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_26_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_25_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_8_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_10_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_10_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_10_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_28_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_27_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_10_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_12_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_12_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_12_CYMUXG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_30_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_29_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_12_XORF : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_14_XORG : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_14_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_32_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_N_31_I : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_14_XORF : STD_LOGIC; 
  signal SDRM_T_INT_LD_RCD_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_PRE_LD_CSLT : STD_LOGIC; 
  signal SDRM_T_INT_PRE_LD_RCD : STD_LOGIC; 
  signal SDRM_T_INT_PRE_LD_BRST : STD_LOGIC; 
  signal SDRM_T_INT_RCD_CNTR_INST_COUNT_SIG_1_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_RCD_CNTR_INST_COUNT_SIG_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_RCD_CNTR_INST_COUNT_SIG_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SD_CAS_OP_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_N_151_I_0 : STD_LOGIC; 
  signal SDRM_T_INT_PRE_SD_CAS_P : STD_LOGIC; 
  signal SD_ADD_OP_1_SRNOT : STD_LOGIC; 
  signal SD_ADD_OP_3_SRNOT : STD_LOGIC; 
  signal SD_WE_OP_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_PRE_SD_RAS_P : STD_LOGIC; 
  signal SDRM_T_INT_PRE_SD_WE_P : STD_LOGIC; 
  signal SD_ADD_OP_5_SRNOT : STD_LOGIC; 
  signal SD_ADD_OP_7_SRNOT : STD_LOGIC; 
  signal SD_ADD_OP_9_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_N_111_I_0 : STD_LOGIC; 
  signal G_39 : STD_LOGIC; 
  signal SD_DOE_NP_1_BYNOT : STD_LOGIC; 
  signal N_72_I : STD_LOGIC; 
  signal SD_ADD_OP_10_SRNOT : STD_LOGIC; 
  signal SDRM_T_INT_N_113_I_0 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_10_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_10_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_10_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_11_FROM : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_11_FFY_SET : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_11_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_RCOUNT_12_FROM : STD_LOGIC;