time_sim.vhd

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

-- Xilinx Vhdl produced by program ngd2vhdl D.24
-- Command: -w sdrm.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Thu Nov  2 14:21:46 2000 
-- Input file: sdrm.nga
-- Output file: time_sim.vhd
-- Tmp file: /var/tmp/xil_CAA0D9jD3
-- Design name: sdrm
-- Xilinx: /export/vol1/extra/tools/xilinx
-- # of Entities: 1
-- Device: v300bg432-6

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity SDRM is
  port (
    CLK_SDP : out STD_LOGIC; 
    SD_WE : out STD_LOGIC; 
    CLK_FBP : in STD_LOGIC := 'X'; 
    WE_RN : in STD_LOGIC := 'X'; 
    SD_CS1 : out STD_LOGIC; 
    SD_CS2 : out STD_LOGIC; 
    CLKP : in STD_LOGIC := 'X'; 
    SD_BA : out STD_LOGIC; 
    DATA_ADDR_N : in STD_LOGIC := 'X'; 
    SD_RAS : out STD_LOGIC; 
    RESET : in STD_LOGIC := 'X'; 
    SD_CAS : out STD_LOGIC; 
    SD_CKE : out STD_LOGIC; 
    SD_DATA : inout STD_LOGIC_VECTOR ( 31 downto 0 ); 
    SD_DQM : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    SD_ADD : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
    AD : inout STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end SDRM;

architecture STRUCTURE of SDRM is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal CLK0A : STD_LOGIC; 
  signal SD_WE_O : STD_LOGIC; 
  signal CLK_FB : STD_LOGIC; 
  signal WE_RN_I : STD_LOGIC; 
  signal CLK : STD_LOGIC; 
  signal SD_BA_O : STD_LOGIC; 
  signal AD_TRI : STD_LOGIC; 
  signal DATA_ADDR_N_I : STD_LOGIC; 
  signal SD_RAS_O : STD_LOGIC; 
  signal RESET_I : STD_LOGIC; 
  signal SD_CAS_O : STD_LOGIC; 
  signal CLK0B : STD_LOGIC; 
  signal CLK_I : STD_LOGIC; 
  signal CLK0C : STD_LOGIC; 
  signal CLK_J : STD_LOGIC; 
  signal LOCKED1 : STD_LOGIC; 
  signal LOCKED2 : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_LCRY : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_COUNT_CRY_1_O : STD_LOGIC; 
  signal SDRM_T_INT_BRST_CNTR_INST_UN1_UN1_LD_BRST_I_0_I : STD_LOGIC; 
  signal SDRM_T_INT_LD_BRST : STD_LOGIC; 
  signal SDRM_T_INT_LOCKED_I : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_N_98_I_0 : STD_LOGIC; 
  signal SDRM_T_INT_KI_CNTR_INST_COUNT_SIG_CRY_1_O : STD_LOGIC; 
  signal SDRM_T_INT_CLR_REF_D : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_1_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_1 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_3_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_3 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_5_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_4 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_5 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_7_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_6 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_7 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_9_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_8 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_9 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_11_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_10 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_11 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_CRY_13_O : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_12 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_13 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_14 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN4_COUNT_N_S_15 : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_5_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_1_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_7_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_6_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_4_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_PRE_SD_READY : STD_LOGIC; 
  signal SDRM_T_INT_LD_RCD : STD_LOGIC; 
  signal SDRM_T_INT_LD_CSLT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_0_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_8_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_10_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_9_Q : STD_LOGIC; 
  signal SD_CAS_OP : STD_LOGIC; 
  signal SDRM_T_INT_SD_ADD_MX : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_11_Q : STD_LOGIC; 
  signal SD_WE_OP : STD_LOGIC; 
  signal SD_RAS_OP : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_2_Q : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_6_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_LOCKED_J : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN3_RCOUNT : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_5_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_5_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_4_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_4_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_3_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_3_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_2_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_2_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_1_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_1_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_32 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_33 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_30 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_G_31 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_16_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_15_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_15_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_14_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_14_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_13_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_13_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_12_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_12_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_11_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_11_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_10_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_10_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_9_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_9_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_8_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_8_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_7_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_REF_MAX_7_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_REF_CNTR_INST_UN1_UN1_RESET_6_0_AND2 : STD_LOGIC; 
  signal SDRM_T_INT_RCD_END : STD_LOGIC; 
  signal SDRM_T_INT_G_65 : STD_LOGIC; 
  signal SDRM_T_INT_BRST_END : STD_LOGIC; 
  signal SDRM_T_INT_CSLT_END : STD_LOGIC; 
  signal SDRM_T_INT_PRE_AD_TRI : STD_LOGIC; 
  signal SDRM_T_INT_KI_END : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_0_12_Q : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_N_154 : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_N_153 : STD_LOGIC; 
  signal SDRM_T_INT_AUTO_REF_OUT : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_N_148 : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_G_70 : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG_3 : STD_LOGIC; 
  signal SYS_INT_INT_LD_CNT_REG : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_STATE_H_G_38 : STD_LOGIC; 
  signal SDRM_T_INT_SDRM_ST_N_126 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal DATA_ADDR_N_REG : STD_LOGIC; 
  signal SD_BA_OP : STD_LOGIC; 
  signal SDRM_T_INT_PRE_LOCKED : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_4 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_5 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_6 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_7 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_8 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_9 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_10 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_11 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_12 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_13 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_14 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_15 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_16 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_17 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_18 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_19 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_20 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_21 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_22 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_23 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_24 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_25 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_26 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_27 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_28 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_29 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_30 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_31 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_32 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_33 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_34 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_35 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_36 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_37 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_38 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_39 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_40 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_41 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_42 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_43 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_44 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_45 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_46 : STD_LOGIC;