time_sim.v

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

    wire \sd_data[6]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[25]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[17]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[7]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[0]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[18]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[26]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[8]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[1]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[27]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[19]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[9]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[2]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[28]/OUTBUF_GTS_AND_1_INV ;
    wire sdr_2_INV;
    wire \AD[3]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[29]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[4]/OUTBUF_GTS_AND_1_INV ;
    wire sdc_2_INV;
    wire \AD[5]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[6]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[7]/OUTBUF_GTS_AND_1_INV ;
    wire sdcke_2_INV;
    wire \AD[8]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[9]/OUTBUF_GTS_AND_1_INV ;
    wire GND;
    wire GSR = glbl.GSR;
    wire VCC;
    wire GTS = glbl.GTS;
    wire [31:0] sd_data_i;
    wire [31:0] sd_data_o;
    wire [31:31] sd_data_t_rep10;
    wire [31:31] sd_data_t_rep11;
    wire [31:31] sd_data_t_rep20;
    wire [31:31] sd_data_t_rep12;
    wire [10:0] sd_add_o;
    wire [31:31] sd_data_t_rep21;
    wire [31:31] sd_data_t_rep13;
    wire [31:31] sd_data_t_rep30;
    wire [31:31] sd_data_t_rep22;
    wire [31:31] sd_data_t_rep14;
    wire [31:31] sd_data_t;
    wire [31:31] sd_data_t_rep23;
    wire [31:31] sd_data_t_rep15;
    wire [31:31] sd_data_t_rep16;
    wire [31:31] sd_data_t_rep24;
    wire [31:31] sd_data_t_rep17;
    wire [31:31] sd_data_t_rep25;
    wire [31:31] sd_data_t_rep26;
    wire [31:31] sd_data_t_rep18;
    wire [31:31] sd_data_t_rep27;
    wire [31:31] sd_data_t_rep19;
    wire [31:31] sd_data_t_rep28;
    wire [31:31] sd_data_t_rep29;
    wire [31:0] ad_i;
    wire [31:0] ad_o;
    wire [31:31] sd_data_t_rep0;
    wire [31:31] sd_data_t_rep1;
    wire [31:31] sd_data_t_rep2;
    wire [31:31] sd_data_t_rep3;
    wire [31:31] sd_data_t_rep4;
    wire [31:31] sd_data_t_rep5;
    wire [31:31] sd_data_t_rep6;
    wire [31:31] sd_data_t_rep7;
    wire [31:31] sd_data_t_rep8;
    wire [31:31] sd_data_t_rep9;
    wire [2:0] sdrm_t_int_brst_cntr_inst_count;
    wire [2:0] burst_max;
    wire [3:0] \sdrm_t_int/ki_cntr_inst/count_sig ;
    wire [3:0] ki_max;
    wire [15:0] \sdrm_t_int/ref_cntr_inst/rcount ;
    wire [1:0] rcd_c_max;
    wire [1:0] sdrm_t_int_rcd_cntr_inst_count_sig;
    wire [21:2] add_reg;
    wire [10:0] sd_add_op;
    wire [3:3] \sdrm_t_int/sd_doe_n_3_i_and2 ;
    wire [1:1] sd_doe_np;
    wire [15:0] ref_max;
    wire [1:0] \sdrm_t_int/cslt_cntr_inst/count_sig ;
    wire [2:0] act_st;
    wire [1:0] cas_lat_max;
    wire [3:3] sd_doe_n;
    wire [31:0] \sys_int_int/data_reg ;
    wire [31:0] sd_data_reg;
    wire [31:0] ad_reg;
    wire [31:0] sd_data_r;
    wire [2:0] \sdrm_t_int/brst_cntr_inst/count_s ;
    wire [2:0] \sdrm_t_int/brst_cntr_inst/count_qxu ;
    wire [3:0] \sdrm_t_int/ki_cntr_inst/count_sig_s ;
    wire [3:0] \sdrm_t_int/ki_cntr_inst/count_sig_qxu ;
    wire [1:0] \sdrm_t_int/rcd_cntr_inst/count_4 ;
    wire [7:0] \sdrm_t_int/sd_add_o_5_1 ;
    wire [15:0] \sdrm_t_int/ref_cntr_inst/count_n ;
    wire [0:0] \sdrm_t_int/sdrm_st/state_h/state_ns_i_i ;
    wire [1:0] \sdrm_t_int/cslt_cntr_inst/count_4 ;
    initial $sdf_annotate("time_sim.sdf");
    X_BUF \iod10/IBUF (
      .I (sd_data[10]),
      .O (\sd_data[10]/IBUF )
    );
    X_INV \sd_data(10)/ENABLEINV (
      .I (sd_data_t_rep10[31]),
      .O (\sd_data[10]/ENABLE )
    );
    X_TRI \iod10/OBUFT (
      .I (\sd_data[10]/OD ),
      .O (sd_data[10]),
      .CTL (\sd_data[10]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(10)/KEEPER (
      .O (\sd_data[10]/KEEPER )
    );
    X_BPAD \sd_data(10)/PAD (
      .PAD (sd_data[10])
    );
    X_BUF \sd_data(10)/IMUX (
      .I (\sd_data[10]/IBUF ),
      .O (sd_data_i[10])
    );
    X_BUF \sd_data(10)/OMUX (
      .I (sd_data_o[10]),
      .O (\sd_data[10]/OD )
    );
    X_AND2 \sd_data(10)/OUTBUF_GTS_AND (
      .I0 (\sd_data[10]/ENABLE ),
      .I1 (\sd_data[10]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[10]/OUTBUF_GTS_AND )
    );
    X_BUF \iod11/IBUF (
      .I (sd_data[11]),
      .O (\sd_data[11]/IBUF )
    );
    X_INV \sd_data(11)/ENABLEINV (
      .I (sd_data_t_rep11[31]),
      .O (\sd_data[11]/ENABLE )
    );
    X_TRI \iod11/OBUFT (
      .I (\sd_data[11]/OD ),
      .O (sd_data[11]),
      .CTL (\sd_data[11]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(11)/KEEPER (
      .O (\sd_data[11]/KEEPER )
    );
    X_BPAD \sd_data(11)/PAD (
      .PAD (sd_data[11])
    );
    X_BUF \sd_data(11)/IMUX (
      .I (\sd_data[11]/IBUF ),
      .O (sd_data_i[11])
    );
    X_BUF \sd_data(11)/OMUX (
      .I (sd_data_o[11]),
      .O (\sd_data[11]/OD )
    );
    X_AND2 \sd_data(11)/OUTBUF_GTS_AND (
      .I0 (\sd_data[11]/ENABLE ),
      .I1 (\sd_data[11]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[11]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_dqm(0)/KEEPER (
      .O (\sd_dqm[0]/KEEPER )
    );
    X_OPAD \sd_dqm(0)/PAD (
      .PAD (sd_dqm[0])
    );
    X_ZERO \sd_dqm(0)/LOGIC_ZERO (
      .O (\sd_dqm[0]/LOGIC_ZERO )
    );
    X_TRI dqm0(
      .I (\sd_dqm[0]/LOGIC_ZERO ),
      .O (sd_dqm[0]),
      .CTL (dqm0_2_INV)
    );
    X_KEEPER \Clk_SDp/KEEPER_0 (
      .O (\Clk_SDp/KEEPER )
    );
    X_OPAD \Clk_SDp/PAD (
      .PAD (Clk_SDp)
    );
    X_BUF \Clk_SDp/OUTMUX_1 (
      .I (clk0a),
      .O (\Clk_SDp/OUTMUX )
    );
    X_TRI obuf0(
      .I (\Clk_SDp/OUTMUX ),
      .O (Clk_SDp),
      .CTL (obuf0_2_INV)
    );
    X_BUF \iod20/IBUF (
      .I (sd_data[20]),
      .O (\sd_data[20]/IBUF )
    );
    X_INV \sd_data(20)/ENABLEINV (
      .I (sd_data_t_rep20[31]),
      .O (\sd_data[20]/ENABLE )
    );
    X_TRI \iod20/OBUFT (
      .I (\sd_data[20]/OUTMUX ),
      .O (sd_data[20]),
      .CTL (\sd_data[20]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(20)/KEEPER (
      .O (\sd_data[20]/KEEPER )
    );
    X_BPAD \sd_data(20)/PAD (
      .PAD (sd_data[20])
    );
    X_BUF \sd_data(20)/IMUX (
      .I (\sd_data[20]/IBUF ),
      .O (sd_data_i[20])
    );
    X_BUF \sd_data(20)/OUTMUX (
      .I (sd_data_o[20]),
      .O (\sd_data[20]/OUTMUX )
    );
    X_AND2 \sd_data(20)/OUTBUF_GTS_AND (
      .I0 (\sd_data[20]/ENABLE ),
      .I1 (\sd_data[20]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[20]/OUTBUF_GTS_AND )
    );
    X_BUF \iod12/IBUF (
      .I (sd_data[12]),
      .O (\sd_data[12]/IBUF )
    );
    X_INV \sd_data(12)/ENABLEINV (
      .I (sd_data_t_rep12[31]),
      .O (\sd_data[12]/ENABLE )
    );
    X_TRI \iod12/OBUFT (
      .I (\sd_data[12]/OD ),
      .O (sd_data[12]),
      .CTL (\sd_data[12]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(12)/KEEPER (
      .O (\sd_data[12]/KEEPER )
    );
    X_BPAD \sd_data(12)/PAD (
      .PAD (sd_data[12])
    );
    X_BUF \sd_data(12)/IMUX (
      .I (\sd_data[12]/IBUF ),
      .O (sd_data_i[12])
    );
    X_BUF \sd_data(12)/OMUX (
      .I (sd_data_o[12]),
      .O (\sd_data[12]/OD )
    );
    X_AND2 \sd_data(12)/OUTBUF_GTS_AND (
      .I0 (\sd_data[12]/ENABLE ),
      .I1 (\sd_data[12]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[12]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_dqm(1)/KEEPER (
      .O (\sd_dqm[1]/KEEPER )
    );
    X_OPAD \sd_dqm(1)/PAD (
      .PAD (sd_dqm[1])
    );
    X_ZERO \sd_dqm(1)/LOGIC_ZERO (
      .O (\sd_dqm[1]/LOGIC_ZERO )
    );
    X_TRI dqm1(
      .I (\sd_dqm[1]/LOGIC_ZERO ),
      .O (sd_dqm[1]),
      .CTL (dqm1_2_INV)
    );
    X_KEEPER \sd_add(0)/KEEPER (
      .O (\sd_add[0]/KEEPER )
    );
    X_OPAD \sd_add(0)/PAD (
      .PAD (sd_add[0])
    );
    X_BUF \sd_add(0)/OMUX (
      .I (sd_add_o[0]),
      .O (\sd_add[0]/OD )
    );
    X_TRI sda0(
      .I (\sd_add[0]/OD ),
      .O (sd_add[0]),
      .CTL (sda0_2_INV)
    );
    X_BUF \iod21/IBUF (
      .I (sd_data[21]),
      .O (\sd_data[21]/IBUF )
    );
    X_INV \sd_data(21)/ENABLEINV (
      .I (sd_data_t_rep21[31]),
      .O (\sd_data[21]/ENABLE )
    );
    X_TRI \iod21/OBUFT (
      .I (\sd_data[21]/OD ),
      .O (sd_data[21]),
      .CTL (\sd_data[21]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(21)/KEEPER (
      .O (\sd_data[21]/KEEPER )
    );
    X_BPAD \sd_data(21)/PAD (
      .PAD (sd_data[21])
    );
    X_BUF \sd_data(21)/IMUX (
      .I (\sd_data[21]/IBUF ),
      .O (sd_data_i[21])
    );
    X_BUF \sd_data(21)/OMUX (
      .I (sd_data_o[21]),
      .O (\sd_data[21]/OD )
    );
    X_AND2 \sd_data(21)/OUTBUF_GTS_AND (
      .I0 (\sd_data[21]/ENABLE ),
      .I1 (\sd_data[21]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[21]/OUTBUF_GTS_AND )
    );
    X_BUF \iod13/IBUF (
      .I (sd_data[13]),
      .O (\sd_data[13]/IBUF )
    );
    X_INV \sd_data(13)/ENABLEINV (
      .I (\sd_data[13]/TORGTS ),
      .O (\sd_data[13]/ENABLE )
    );
    X_TRI \iod13/OBUFT (
      .I (\sd_data[13]/OD ),
      .O (sd_data[13]),
      .CTL (\sd_data[13]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_data(13)/KEEPER (
      .O (\sd_data[13]/KEEPER )
    );
    X_BPAD \sd_data(13)/PAD (
      .PAD (sd_data[13])
    );
    X_BUF \sd_data(13)/IMUX (
      .I (\sd_data[13]/IBUF ),
      .O (sd_data_i[13])
    );
    X_BUF \sd_data(13)/OMUX (
      .I (sd_data_o[13]),
      .O (\sd_data[13]/OD )
    );
    X_BUF \sd_data(13)/GTS_OR (
      .I (sd_data_t_rep13[31]),
      .O (\sd_data[13]/TORGTS )
    );
    X_AND2 \sd_data(13)/OUTBUF_GTS_AND (
      .I0 (\sd_data[13]/ENABLE ),
      .I1 (\sd_data[13]/OUTBUF_GTS_AND_1_INV ),
      .O (\sd_data[13]/OUTBUF_GTS_AND )
    );
    X_KEEPER \sd_dqm(2)/KEEPER (
      .O (\sd_dqm[2]/KEEPER )
    );
    X_OPAD \sd_dqm(2)/PAD (
      .PAD (sd_dqm[2])
    );
    X_ZERO \sd_dqm(2)/LOGIC_ZERO (
      .O (\sd_dqm[2]/LOGIC_ZERO )
    );
    X_TRI dqm2(
      .I (\sd_dqm[2]/LOGIC_ZERO ),
      .O (sd_dqm[2]),
      .CTL (dqm2_2_INV)
    );
    X_KEEPER \sd_add(1)/KEEPER (
      .O (\sd_add[1]/KEEP