time_sim.v

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

    wire \sd_data_r[11]/SRNOT ;
    wire \sd_data_r[11]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[11]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[21]/SRNOT ;
    wire \sd_data_r[21]/FROM ;
    wire \sd_data_r[21]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[21]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[13]/SRNOT ;
    wire \sd_data_r[13]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[13]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[31]/SRNOT ;
    wire \sd_data_r[31]/GROM ;
    wire \sd_data_r[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[31]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[23]/SRNOT ;
    wire \sd_data_r[23]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[23]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[15]/SRNOT ;
    wire \sd_data_r[15]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[15]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[25]/SRNOT ;
    wire \sd_data_r[25]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[25]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[17]/SRNOT ;
    wire \sd_data_r[17]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[17]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[27]/SRNOT ;
    wire \sd_data_r[27]/GROM ;
    wire \sd_data_r[27]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[27]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[19]/SRNOT ;
    wire \sd_data_r[19]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[19]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[29]/SRNOT ;
    wire \sd_data_r[29]/GROM ;
    wire \sd_data_r[29]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_r[29]/FFX/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_2_0_and2/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_2_0_and2/FROM ;
    wire \sd_data_reg[25]/LOGIC_ONE ;
    wire \sd_data_reg[25]/GSHIFT ;
    wire \sd_data_reg[25]/FROM ;
    wire \sd_data_reg[17]/LOGIC_ONE ;
    wire \sd_data_reg[17]/GSHIFT ;
    wire \sd_data_reg[17]/FROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_10_0_and2/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_10_0_and2/FROM ;
    wire \sd_data_t[31]/SRNOT ;
    wire \sd_data_t[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_doe_n[3]/SRNOT ;
    wire \sd_doe_n[3]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[11]/CENOT ;
    wire \add_reg[11]/SRNOT ;
    wire \add_reg[11]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[11]/FFX/ASYNC_FF_GSR_OR ;
    wire \add_reg[21]/CENOT ;
    wire \add_reg[21]/SRNOT ;
    wire \add_reg[21]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[21]/FFX/ASYNC_FF_GSR_OR ;
    wire \add_reg[13]/CENOT ;
    wire \add_reg[13]/SRNOT ;
    wire \add_reg[13]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[13]/FFX/ASYNC_FF_GSR_OR ;
    wire \add_reg[15]/CENOT ;
    wire \add_reg[15]/SRNOT ;
    wire \add_reg[15]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[15]/FFX/ASYNC_FF_GSR_OR ;
    wire \add_reg[17]/CENOT ;
    wire \add_reg[17]/SRNOT ;
    wire \add_reg[17]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[17]/FFX/ASYNC_FF_GSR_OR ;
    wire \add_reg[19]/CENOT ;
    wire \add_reg[19]/SRNOT ;
    wire \add_reg[19]/FFY/ASYNC_FF_GSR_OR ;
    wire \add_reg[19]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_ba_o/SRNOT ;
    wire \sd_ba_o/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/brst_cntr_inst/count_lcry/GROM ;
    wire \sdrm_t_int/brst_cntr_inst/count_lcry/FROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_0_and2/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_0_and2/FROM ;
    wire \sd_data_reg[6]/LOGIC_ONE ;
    wire \sd_data_reg[6]/GSHIFT ;
    wire \sd_data_reg[6]/FROM ;
    wire \sd_data_reg[10]/LOGIC_ONE ;
    wire \sd_data_reg[10]/GSHIFT ;
    wire \sd_data_reg[10]/FROM ;
    wire \sd_data_reg[26]/LOGIC_ONE ;
    wire \sd_data_reg[26]/GSHIFT ;
    wire \sd_data_reg[26]/FROM ;
    wire \sd_data_reg[18]/LOGIC_ONE ;
    wire \sd_data_reg[18]/GSHIFT ;
    wire \ad_o[11]/SRNOT ;
    wire \ad_o[11]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[11]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[21]/SRNOT ;
    wire \ad_o[21]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[21]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[13]/SRNOT ;
    wire \ad_o[13]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[13]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[31]/SRNOT ;
    wire \ad_o[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[31]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[23]/SRNOT ;
    wire \ad_o[23]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[23]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[15]/SRNOT ;
    wire \ad_o[15]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[15]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[25]/SRNOT ;
    wire \ad_o[25]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[25]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[17]/SRNOT ;
    wire \ad_o[17]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[17]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[27]/SRNOT ;
    wire \ad_o[27]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[27]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[19]/SRNOT ;
    wire \ad_o[19]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[19]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_o[29]/SRNOT ;
    wire \ad_o[29]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_o[29]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_tri/LOGIC_ONE ;
    wire \ad_tri/GSHIFT ;
    wire \ad_tri/FROM ;
    wire \cas_lat_max[1]/SRNOT ;
    wire \cas_lat_max[1]/FFY/ASYNC_FF_GSR_OR ;
    wire \cas_lat_max[1]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep10[31]/SRNOT ;
    wire \sd_data_t_rep10[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \rcd_c_max[1]/SRNOT ;
    wire \rcd_c_max[1]/FFY/ASYNC_FF_GSR_OR ;
    wire \rcd_c_max[1]/FFX/ASYNC_FF_GSR_OR ;
    wire \burst_max[1]/SRNOT ;
    wire \burst_max[1]/FFY/ASYNC_FF_GSR_OR ;
    wire \burst_max[1]/FFX/ASYNC_FF_GSR_OR ;
    wire \burst_max[2]/SRNOT ;
    wire \burst_max[2]/FFY/ASYNC_FF_GSR_OR ;
    wire \ref_max[1]/SRNOT ;
    wire \ref_max[1]/FFY/ASYNC_FF_GSR_OR ;
    wire \ref_max[1]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep11[31]/SRNOT ;
    wire \sd_data_t_rep11[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep20[31]/SRNOT ;
    wire \sd_data_t_rep20[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep12[31]/SRNOT ;
    wire \sd_data_t_rep12[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[7]/LOGIC_ONE ;
    wire \sd_data_reg[7]/GSHIFT ;
    wire \sd_we_o/SRNOT ;
    wire \sd_we_o/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep21[31]/SRNOT ;
    wire \sd_data_t_rep21[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep13[31]/SRNOT ;
    wire \sd_data_t_rep13[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_15_0_and2/GROM ;
    wire \sd_add_o[10]/SRNOT ;
    wire \sd_add_o[10]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep30[31]/SRNOT ;
    wire \sd_data_t_rep30[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep22[31]/SRNOT ;
    wire \sd_data_t_rep22[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep14[31]/SRNOT ;
    wire \sd_data_t_rep14[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[11]/LOGIC_ONE ;
    wire \sd_data_reg[11]/GSHIFT ;
    wire \sd_data_reg[11]/FROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_4_0_and2/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_4_0_and2/FROM ;
    wire \sd_data_t_rep23[31]/SRNOT ;
    wire \sd_data_t_rep23[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep15[31]/SRNOT ;
    wire \sd_data_t_rep15[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[27]/LOGIC_ONE ;
    wire \sd_data_reg[27]/GSHIFT ;
    wire \sd_data_reg[19]/LOGIC_ONE ;
    wire \sd_data_reg[19]/GSHIFT ;
    wire \sd_data_t_rep24[31]/SRNOT ;
    wire \sd_data_t_rep24[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep16[31]/SRNOT ;
    wire \sd_data_t_rep16[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep25[31]/SRNOT ;
    wire \sd_data_t_rep25[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep17[31]/SRNOT ;
    wire \sd_data_t_rep17[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/locked_j/LOGIC_ONE ;
    wire \sdrm_t_int/locked_j/GSHIFT ;
    wire \sdrm_t_int/locked_j/FROM ;
    wire \sd_data_t_rep26[31]/SRNOT ;
    wire \sd_data_t_rep26[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep18[31]/SRNOT ;
    wire \sd_data_t_rep18[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/pre_locked/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/G_30/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/G_31/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/G_32/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/G_33/GROM ;
    wire \sd_data_t_rep27[31]/SRNOT ;
    wire \sd_data_t_rep27[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep19[31]/SRNOT ;
    wire \sd_data_t_rep19[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[0]/LOGIC_ONE ;
    wire \sd_data_reg[0]/GSHIFT ;
    wire \sd_data_reg[0]/FROM ;
    wire \sd_data_t_rep28[31]/SRNOT ;
    wire \sd_data_t_rep28[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[8]/LOGIC_ONE ;
    wire \sd_data_reg[8]/GSHIFT ;
    wire \sd_data_reg[8]/FROM ;
    wire \sd_data_t_rep29[31]/SRNOT ;
    wire \sd_data_t_rep29[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[20]/LOGIC_ONE ;
    wire \sd_data_reg[20]/GSHIFT ;
    wire \sd_data_reg[12]/LOGIC_ONE ;
    wire \sd_data_reg[12]/GSHIFT ;
    wire \sd_data_reg[28]/LOGIC_ONE ;
    wire \sd_data_reg[28]/GSHIFT ;
    wire \sdrm_t_int/auto_ref_out/LOGIC_ONE ;
    wire \sdrm_t_int/auto_ref_out/SRNOT ;
    wire \sdrm_t_int/auto_ref_out/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[11]/SRNOT ;
    wire \ad_reg[11]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[11]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[21]/SRNOT ;
    wire \ad_reg[21]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[21]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[13]/SRNOT ;
    wire \ad_reg[13]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[13]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[31]/SRNOT ;
    wire \ad_reg[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[31]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[23]/SRNOT ;
    wire \ad_reg[23]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[23]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[15]/SRNOT ;
    wire \ad_reg[15]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[15]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[25]/SRNOT ;
    wire \ad_reg[25]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[25]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[17]/SRNOT ;
    wire \ad_reg[17]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[17]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[27]/SRNOT ;
    wire \ad_reg[27]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[27]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[19]/SRNOT ;
    wire \ad_reg[19]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[19]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[29]/SRNOT ;
    wire \ad_reg[29]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[29]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[1]/LOGIC_ONE ;
    wire \sd_data_reg[1]/GSHIFT ;
    wire \sd_data_reg[9]/LOGIC_ONE ;
    wire \sd_data_reg[9]/GSHIFT ;
    wire \sd_data_reg[9]/FROM ;
    wire \sd_data_reg[21]/LOGIC_ONE ;
    wire \sd_data_reg[21]/GSHIFT ;
    wire \sd_data_reg[13]/LOGIC_ONE ;
    wire \sd_data_reg[13]/GSHIFT ;
    wire \sd_data_reg[13]/FROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_6_0_and2/GROM ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_6_0_and2/FROM ;
    wire \ad_reg[1]/SRNOT ;
    wire \ad_reg[1]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[1]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_reg[29]/LOGIC_ONE ;
    wire \sd_data_reg[29]/GSHIFT ;
    wire \sd_data_reg[29]/FROM ;
    wire \ad_reg[3]/SRNOT ;
    wire \ad_reg[3]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[3]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[5]/SRNOT ;
    wire \ad_reg[5]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[5]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[7]/SRNOT ;
    wire \ad_reg[7]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[7]/FFX/ASYNC_FF_GSR_OR ;
    wire \ad_reg[9]/SRNOT ;
    wire \ad_reg[9]/FFY/ASYNC_FF_GSR_OR ;
    wire \ad_reg[9]/FFX/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep0[31]/SRNOT ;
    wire \sd_data_t_rep0[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep1[31]/SRNOT ;
    wire \sd_data_t_rep1[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/sdrm_st/N_126/GROM ;
    wire \sdrm_t_int/sdrm_st/N_126/FROM ;
    wire \sd_data_reg[2]/LOGIC_ONE ;
    wire \sd_data_reg[2]/GSHIFT ;
    wire \sd_data_t_rep2[31]/SRNOT ;
    wire \sd_data_t_rep2[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \sd_data_t_rep3[31]/SRNOT ;
    wire \sd_data_t_rep3[31]/FFY/ASYNC_FF_GSR_OR ;
    wire \act_st[2]/BYNOT ;
    wire \dll0/CLK0 ;
    wire \dll0/CLK180 ;
    wire \dll0/CLK270 ;
    wire \dll0/CLK90 ;
    wire \dll0/CLKDV ;
    wire \dll1/CLK180 ;
    wire \dll1/CLK270 ;
    wire \dll1/CLK90 ;
    wire \dll1/CLKDV ;
    wire \sd_data[10]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[11]/OUTBUF_GTS_AND_1_INV ;
    wire dqm0_2_INV;
    wire obuf0_2_INV;
    wire \sd_data[20]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[12]/OUTBUF_GTS_AND_1_INV ;
    wire dqm1_2_INV;
    wire sda0_2_INV;
    wire \sd_data[21]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[13]/OUTBUF_GTS_AND_1_INV ;
    wire dqm2_2_INV;
    wire sda1_2_INV;
    wire sdw_2_INV;
    wire \sd_data[30]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[22]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[14]/OUTBUF_GTS_AND_1_INV ;
    wire dqm3_2_INV;
    wire sda2_2_INV;
    wire \sd_data[31]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[23]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[15]/OUTBUF_GTS_AND_1_INV ;
    wire sda3_2_INV;
    wire \sd_data[16]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[24]/OUTBUF_GTS_AND_1_INV ;
    wire sda4_2_INV;
    wire sda10_2_INV;
    wire \sd_data[17]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[25]/OUTBUF_GTS_AND_1_INV ;
    wire sda5_2_INV;
    wire \sd_data[26]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[18]/OUTBUF_GTS_AND_1_INV ;
    wire sda6_2_INV;
    wire \sd_data[27]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[19]/OUTBUF_GTS_AND_1_INV ;
    wire sda7_2_INV;
    wire \sd_data[28]/OUTBUF_GTS_AND_1_INV ;
    wire sda8_2_INV;
    wire sdcs1_2_INV;
    wire \sd_data[29]/OUTBUF_GTS_AND_1_INV ;
    wire sdcs2_2_INV;
    wire sda9_2_INV;
    wire sdb_2_INV;
    wire \AD[10]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[0]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[11]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[1]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[12]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[20]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[2]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[13]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[21]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[3]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[30]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[14]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[22]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[4]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[31]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[15]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[23]/OUTBUF_GTS_AND_1_INV ;
    wire \sd_data[5]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[16]/OUTBUF_GTS_AND_1_INV ;
    wire \AD[24]/OUTBUF_GTS_AND_1_INV ;