time_sim.v

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

    wire \sd_data[25]/IBUF ;
    wire \sd_data[25]/OUTMUX ;
    wire \sd_data[25]/ENABLE ;
    wire \sd_data[25]/KEEPER ;
    wire \sd_data[25]/OUTBUF_GTS_AND ;
    wire \sd_add[5]/OD ;
    wire \sd_add[5]/KEEPER ;
    wire \we_rn/IBUF ;
    wire \we_rn/KEEPER ;
    wire \sd_data[26]/IBUF ;
    wire \sd_data[26]/OD ;
    wire \sd_data[26]/ENABLE ;
    wire \sd_data[26]/KEEPER ;
    wire \sd_data[26]/OUTBUF_GTS_AND ;
    wire \sd_data[18]/IBUF ;
    wire \sd_data[18]/OD ;
    wire \sd_data[18]/ENABLE ;
    wire \sd_data[18]/KEEPER ;
    wire \sd_data[18]/OUTBUF_GTS_AND ;
    wire \sd_add[6]/OD ;
    wire \sd_add[6]/KEEPER ;
    wire \sd_data[27]/IBUF ;
    wire \sd_data[27]/OUTMUX ;
    wire \sd_data[27]/ENABLE ;
    wire \sd_data[27]/KEEPER ;
    wire \sd_data[27]/OUTBUF_GTS_AND ;
    wire \sd_data[19]/IBUF ;
    wire \sd_data[19]/OD ;
    wire \sd_data[19]/ENABLE ;
    wire \sd_data[19]/KEEPER ;
    wire \sd_data[19]/OUTBUF_GTS_AND ;
    wire \sd_add[7]/OD ;
    wire \sd_add[7]/KEEPER ;
    wire \sd_data[28]/IBUF ;
    wire \sd_data[28]/OUTMUX ;
    wire \sd_data[28]/TORGTS ;
    wire \sd_data[28]/ENABLE ;
    wire \sd_data[28]/KEEPER ;
    wire \sd_data[28]/OUTBUF_GTS_AND ;
    wire \sd_add[8]/OUTMUX ;
    wire \sd_add[8]/KEEPER ;
    wire \sd_cs1/LOGIC_ZERO ;
    wire \sd_cs1/KEEPER ;
    wire \sd_data[29]/IBUF ;
    wire \sd_data[29]/OUTMUX ;
    wire \sd_data[29]/ENABLE ;
    wire \sd_data[29]/KEEPER ;
    wire \sd_data[29]/OUTBUF_GTS_AND ;
    wire \sd_cs2/LOGIC_ZERO ;
    wire \sd_cs2/KEEPER ;
    wire \sd_add[9]/OUTMUX ;
    wire \sd_add[9]/KEEPER ;
    wire \sd_ba/OD ;
    wire \sd_ba/KEEPER ;
    wire \AD[10]/IBUF ;
    wire \AD[10]/OD ;
    wire \AD[10]/TORGTS ;
    wire \AD[10]/ENABLE ;
    wire \AD[10]/KEEPER ;
    wire \AD[10]/OUTBUF_GTS_AND ;
    wire \sd_data[0]/IBUF ;
    wire \sd_data[0]/OUTMUX ;
    wire \sd_data[0]/ENABLE ;
    wire \sd_data[0]/KEEPER ;
    wire \sd_data[0]/OUTBUF_GTS_AND ;
    wire \AD[11]/IBUF ;
    wire \AD[11]/OD ;
    wire \AD[11]/TORGTS ;
    wire \AD[11]/ENABLE ;
    wire \AD[11]/KEEPER ;
    wire \AD[11]/OUTBUF_GTS_AND ;
    wire \sd_data[1]/IBUF ;
    wire \sd_data[1]/OUTMUX ;
    wire \sd_data[1]/ENABLE ;
    wire \sd_data[1]/KEEPER ;
    wire \sd_data[1]/OUTBUF_GTS_AND ;
    wire \AD[12]/IBUF ;
    wire \AD[12]/OUTMUX ;
    wire \AD[12]/TORGTS ;
    wire \AD[12]/ENABLE ;
    wire \AD[12]/KEEPER ;
    wire \AD[12]/OUTBUF_GTS_AND ;
    wire \AD[20]/IBUF ;
    wire \AD[20]/OD ;
    wire \AD[20]/TORGTS ;
    wire \AD[20]/ENABLE ;
    wire \AD[20]/KEEPER ;
    wire \AD[20]/OUTBUF_GTS_AND ;
    wire \sd_data[2]/IBUF ;
    wire \sd_data[2]/OD ;
    wire \sd_data[2]/ENABLE ;
    wire \sd_data[2]/KEEPER ;
    wire \sd_data[2]/OUTBUF_GTS_AND ;
    wire \AD[13]/IBUF ;
    wire \AD[13]/OUTMUX ;
    wire \AD[13]/TORGTS ;
    wire \AD[13]/ENABLE ;
    wire \AD[13]/KEEPER ;
    wire \AD[13]/OUTBUF_GTS_AND ;
    wire \AD[21]/IBUF ;
    wire \AD[21]/OD ;
    wire \AD[21]/TORGTS ;
    wire \AD[21]/ENABLE ;
    wire \AD[21]/KEEPER ;
    wire \AD[21]/OUTBUF_GTS_AND ;
    wire \sd_data[3]/IBUF ;
    wire \sd_data[3]/OD ;
    wire \sd_data[3]/ENABLE ;
    wire \sd_data[3]/KEEPER ;
    wire \sd_data[3]/OUTBUF_GTS_AND ;
    wire \AD[30]/IBUF ;
    wire \AD[30]/OD ;
    wire \AD[30]/TORGTS ;
    wire \AD[30]/ENABLE ;
    wire \AD[30]/KEEPER ;
    wire \AD[30]/OUTBUF_GTS_AND ;
    wire \AD[14]/IBUF ;
    wire \AD[14]/OD ;
    wire \AD[14]/TORGTS ;
    wire \AD[14]/ENABLE ;
    wire \AD[14]/KEEPER ;
    wire \AD[14]/OUTBUF_GTS_AND ;
    wire \AD[22]/IBUF ;
    wire \AD[22]/OD ;
    wire \AD[22]/TORGTS ;
    wire \AD[22]/ENABLE ;
    wire \AD[22]/KEEPER ;
    wire \AD[22]/OUTBUF_GTS_AND ;
    wire \sd_data[4]/IBUF ;
    wire \sd_data[4]/OUTMUX ;
    wire \sd_data[4]/ENABLE ;
    wire \sd_data[4]/KEEPER ;
    wire \sd_data[4]/OUTBUF_GTS_AND ;
    wire \AD[31]/IBUF ;
    wire \AD[31]/OD ;
    wire \AD[31]/TORGTS ;
    wire \AD[31]/ENABLE ;
    wire \AD[31]/KEEPER ;
    wire \AD[31]/OUTBUF_GTS_AND ;
    wire \AD[15]/IBUF ;
    wire \AD[15]/OD ;
    wire \AD[15]/TORGTS ;
    wire \AD[15]/ENABLE ;
    wire \AD[15]/KEEPER ;
    wire \AD[15]/OUTBUF_GTS_AND ;
    wire \AD[23]/IBUF ;
    wire \AD[23]/OD ;
    wire \AD[23]/TORGTS ;
    wire \AD[23]/ENABLE ;
    wire \AD[23]/KEEPER ;
    wire \AD[23]/OUTBUF_GTS_AND ;
    wire \sd_data[5]/IBUF ;
    wire \sd_data[5]/OD ;
    wire \sd_data[5]/ENABLE ;
    wire \sd_data[5]/KEEPER ;
    wire \sd_data[5]/OUTBUF_GTS_AND ;
    wire \AD[16]/IBUF ;
    wire \AD[16]/OD ;
    wire \AD[16]/TORGTS ;
    wire \AD[16]/ENABLE ;
    wire \AD[16]/KEEPER ;
    wire \AD[16]/OUTBUF_GTS_AND ;
    wire \AD[24]/IBUF ;
    wire \AD[24]/OD ;
    wire \AD[24]/TORGTS ;
    wire \AD[24]/ENABLE ;
    wire \AD[24]/KEEPER ;
    wire \AD[24]/OUTBUF_GTS_AND ;
    wire \data_addr_n/IBUF ;
    wire \data_addr_n/KEEPER ;
    wire \sd_data[6]/IBUF ;
    wire \sd_data[6]/OD ;
    wire \sd_data[6]/ENABLE ;
    wire \sd_data[6]/KEEPER ;
    wire \sd_data[6]/OUTBUF_GTS_AND ;
    wire \AD[25]/IBUF ;
    wire \AD[25]/OD ;
    wire \AD[25]/TORGTS ;
    wire \AD[25]/ENABLE ;
    wire \AD[25]/KEEPER ;
    wire \AD[25]/OUTBUF_GTS_AND ;
    wire \AD[17]/IBUF ;
    wire \AD[17]/OD ;
    wire \AD[17]/TORGTS ;
    wire \AD[17]/ENABLE ;
    wire \AD[17]/KEEPER ;
    wire \AD[17]/OUTBUF_GTS_AND ;
    wire \sd_data[7]/IBUF ;
    wire \sd_data[7]/OD ;
    wire \sd_data[7]/ENABLE ;
    wire \sd_data[7]/KEEPER ;
    wire \sd_data[7]/OUTBUF_GTS_AND ;
    wire \AD[0]/IBUF ;
    wire \AD[0]/OD ;
    wire \AD[0]/TORGTS ;
    wire \AD[0]/ENABLE ;
    wire \AD[0]/KEEPER ;
    wire \AD[0]/OUTBUF_GTS_AND ;
    wire \AD[18]/IBUF ;
    wire \AD[18]/OUTMUX ;
    wire \AD[18]/TORGTS ;
    wire \AD[18]/ENABLE ;
    wire \AD[18]/KEEPER ;
    wire \AD[18]/OUTBUF_GTS_AND ;
    wire \AD[26]/IBUF ;
    wire \AD[26]/OD ;
    wire \AD[26]/TORGTS ;
    wire \AD[26]/ENABLE ;
    wire \AD[26]/KEEPER ;
    wire \AD[26]/OUTBUF_GTS_AND ;
    wire \sd_data[8]/IBUF ;
    wire \sd_data[8]/OUTMUX ;
    wire \sd_data[8]/ENABLE ;
    wire \sd_data[8]/KEEPER ;
    wire \sd_data[8]/OUTBUF_GTS_AND ;
    wire \AD[1]/IBUF ;
    wire \AD[1]/OD ;
    wire \AD[1]/TORGTS ;
    wire \AD[1]/ENABLE ;
    wire \AD[1]/KEEPER ;
    wire \AD[1]/OUTBUF_GTS_AND ;
    wire \AD[27]/IBUF ;
    wire \AD[27]/OD ;
    wire \AD[27]/TORGTS ;
    wire \AD[27]/ENABLE ;
    wire \AD[27]/KEEPER ;
    wire \AD[27]/OUTBUF_GTS_AND ;
    wire \AD[19]/IBUF ;
    wire \AD[19]/OUTMUX ;
    wire \AD[19]/TORGTS ;
    wire \AD[19]/ENABLE ;
    wire \AD[19]/KEEPER ;
    wire \AD[19]/OUTBUF_GTS_AND ;
    wire \sd_data[9]/IBUF ;
    wire \sd_data[9]/OUTMUX ;
    wire \sd_data[9]/ENABLE ;
    wire \sd_data[9]/KEEPER ;
    wire \sd_data[9]/OUTBUF_GTS_AND ;
    wire \AD[2]/IBUF ;
    wire \AD[2]/OD ;
    wire \AD[2]/TORGTS ;
    wire \AD[2]/ENABLE ;
    wire \AD[2]/KEEPER ;
    wire \AD[2]/OUTBUF_GTS_AND ;
    wire \AD[28]/IBUF ;
    wire \AD[28]/OUTMUX ;
    wire \AD[28]/TORGTS ;
    wire \AD[28]/ENABLE ;
    wire \AD[28]/KEEPER ;
    wire \AD[28]/OUTBUF_GTS_AND ;
    wire \sd_ras/OD ;
    wire \sd_ras/KEEPER ;
    wire \AD[3]/IBUF ;
    wire \AD[3]/OD ;
    wire \AD[3]/TORGTS ;
    wire \AD[3]/ENABLE ;
    wire \AD[3]/KEEPER ;
    wire \AD[3]/OUTBUF_GTS_AND ;
    wire \AD[29]/IBUF ;
    wire \AD[29]/OUTMUX ;
    wire \AD[29]/TORGTS ;
    wire \AD[29]/ENABLE ;
    wire \AD[29]/KEEPER ;
    wire \AD[29]/OUTBUF_GTS_AND ;
    wire \Reset/IBUF ;
    wire \Reset/KEEPER ;
    wire \AD[4]/IBUF ;
    wire \AD[4]/OD ;
    wire \AD[4]/TORGTS ;
    wire \AD[4]/ENABLE ;
    wire \AD[4]/KEEPER ;
    wire \AD[4]/OUTBUF_GTS_AND ;
    wire \sd_cas/OD ;
    wire \sd_cas/KEEPER ;
    wire \AD[5]/IBUF ;
    wire \AD[5]/OD ;
    wire \AD[5]/TORGTS ;
    wire \AD[5]/ENABLE ;
    wire \AD[5]/KEEPER ;
    wire \AD[5]/OUTBUF_GTS_AND ;
    wire \AD[6]/IBUF ;
    wire \AD[6]/OD ;
    wire \AD[6]/TORGTS ;
    wire \AD[6]/ENABLE ;
    wire \AD[6]/KEEPER ;
    wire \AD[6]/OUTBUF_GTS_AND ;
    wire \AD[7]/IBUF ;
    wire \AD[7]/OD ;
    wire \AD[7]/TORGTS ;
    wire \AD[7]/ENABLE ;
    wire \AD[7]/KEEPER ;
    wire \AD[7]/OUTBUF_GTS_AND ;
    wire \sd_cke/LOGIC_ONE ;
    wire \sd_cke/KEEPER ;
    wire \AD[8]/IBUF ;
    wire \AD[8]/OD ;
    wire \AD[8]/TORGTS ;
    wire \AD[8]/ENABLE ;
    wire \AD[8]/KEEPER ;
    wire \AD[8]/OUTBUF_GTS_AND ;
    wire \AD[9]/IBUF ;
    wire \AD[9]/OD ;
    wire \AD[9]/TORGTS ;
    wire \AD[9]/ENABLE ;
    wire \AD[9]/KEEPER ;
    wire \AD[9]/OUTBUF_GTS_AND ;
    wire \sdrm_t_int_brst_cntr_inst_count[0]/SRNOT ;
    wire \sdrm_t_int/brst_cntr_inst/count_cry[0]/O ;
    wire \sdrm_t_int_brst_cntr_inst_count[0]/LOGIC_ONE ;
    wire \sdrm_t_int_brst_cntr_inst_count[0]/CYMUXG ;
    wire \sdrm_t_int_brst_cntr_inst_count[0]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int_brst_cntr_inst_count[0]/FFX/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int_brst_cntr_inst_count[2]/SRNOT ;
    wire \sdrm_t_int_brst_cntr_inst_count[2]/GROM ;
    wire \sdrm_t_int_brst_cntr_inst_count[2]/FFX/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[0]/SRNOT ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig_cry[0]/O ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[0]/LOGIC_ONE ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[0]/CYMUXG ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[0]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[0]/FFX/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[2]/SRNOT ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig_cry[2]/O ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[2]/LOGIC_ONE ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[2]/FFY/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig[2]/FFX/ASYNC_FF_GSR_OR ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_1/LOGIC_ZERO ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_1/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_0/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_1/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_18_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_17_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_2/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_2/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_2/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_20_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_19_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_2/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_4/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_4/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_4/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_22_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_21_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_4/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_6/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_6/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_6/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_24_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_23_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_6/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_8/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_8/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_8/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_26_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_25_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_8/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_10/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_10/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_10/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_28_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_27_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_10/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_12/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_12/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_12/CYMUXG ;
    wire \sdrm_t_int/ref_cntr_inst/N_30_i ;
    wire \sdrm_t_int/ref_cntr_inst/N_29_i ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_12/XORF ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_14/XORG ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_14/O ;