time_sim.v

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

// Xilinx Verilog produced by program ngd2ver D.24
// Command: -w sdrm.nga time_sim.v 
// Options: -w -log ngd2ver.log -ti uut 
// Date: Thu Nov  2 14:18:01 2000 
// Input file: sdrm.nga
// Output file: time_sim.v
// Tmp file: /var/tmp/xil_CAA0Cde_P
// Design name: sdrm
// Xilinx: /export/vol1/extra/tools/xilinx
// # of Modules: 1
// Device: v300bg432-6

// The output of ngd2ver is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/1 ps

  module sdrm (
    Clk_SDp, sd_we, Clk_FBp, we_rn, sd_cs1, sd_cs2, Clkp, sd_ba, data_addr_n, 
    sd_ras, Reset, sd_cas, sd_cke, sd_data, sd_dqm, sd_add, AD
  );
    output Clk_SDp;
    output sd_we;
    input Clk_FBp;
    input we_rn;
    output sd_cs1;
    output sd_cs2;
    input Clkp;
    output sd_ba;
    input data_addr_n;
    output sd_ras;
    input Reset;
    output sd_cas;
    output sd_cke;
    inout [31:0] sd_data;
    output [3:0] sd_dqm;
    output [10:0] sd_add;
    inout [31:0] AD;
    wire XON;
    wire clk0a;
    wire sd_we_o;
    wire clk_fb;
    wire we_rn_i;
    wire clk;
    wire sd_ba_o;
    wire ad_tri;
    wire data_addr_n_i;
    wire sd_ras_o;
    wire reset_i;
    wire sd_cas_o;
    wire clk0b;
    wire clk_i;
    wire clk0c;
    wire clk_j;
    wire locked1;
    wire locked2;
    wire \sdrm_t_int/brst_cntr_inst/count_lcry ;
    wire \sdrm_t_int/brst_cntr_inst/count_cry[1]/O ;
    wire sdrm_t_int_brst_cntr_inst_un1_un1_ld_brst_i_0_i;
    wire sdrm_t_int_ld_brst;
    wire \sdrm_t_int/locked_i ;
    wire \sdrm_t_int/ki_cntr_inst/N_98_i_0 ;
    wire \sdrm_t_int/ki_cntr_inst/count_sig_cry[1]/O ;
    wire \sdrm_t_int/clr_ref_d ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_1/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_1 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_3/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_2 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_3 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_5/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_4 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_5 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_7/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_6 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_7 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_9/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_8 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_9 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_11/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_10 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_11 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_cry_13/O ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_12 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_13 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_14 ;
    wire \sdrm_t_int/ref_cntr_inst/un4_count_n_s_15 ;
    wire \sdrm_t_int/sdrm_st/state_0[5] ;
    wire \sdrm_t_int/sdrm_st/state_0[1] ;
    wire \sdrm_t_int_sdrm_st_state[7] ;
    wire \sdrm_t_int/sdrm_st/state_0[6] ;
    wire \sdrm_t_int/sdrm_st/state_0[4] ;
    wire \sdrm_t_int/sdrm_st/pre_sd_ready ;
    wire \sdrm_t_int/ld_rcd ;
    wire \sdrm_t_int/ld_cslt ;
    wire \sdrm_t_int/sdrm_st/state_0[0] ;
    wire \sdrm_t_int/sdrm_st/state_0[8] ;
    wire \sdrm_t_int/sdrm_st/state_0[10] ;
    wire \sdrm_t_int/sdrm_st/state_0[9] ;
    wire sd_cas_op;
    wire sdrm_t_int_sd_add_mx;
    wire \sdrm_t_int/sdrm_st/state_0[11] ;
    wire sd_we_op;
    wire sd_ras_op;
    wire \sdrm_t_int_sdrm_st_state[2] ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_6_0_and2 ;
    wire \sdrm_t_int/locked_j ;
    wire \sdrm_t_int/ref_cntr_inst/un3_rcount ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_5_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_5_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_4_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_4_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_3_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_3_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_2_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_2_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_1_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_1_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/G_32 ;
    wire \sdrm_t_int/ref_cntr_inst/G_33 ;
    wire \sdrm_t_int/ref_cntr_inst/G_30 ;
    wire \sdrm_t_int/ref_cntr_inst/G_31 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_16_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_15_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_15_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_14_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_14_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_13_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_13_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_12_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_12_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_11_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_11_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_10_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_10_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_9_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_9_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_8_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_8_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_7_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_ref_max_7_0_and2 ;
    wire \sdrm_t_int/ref_cntr_inst/un1_un1_reset_6_0_and2 ;
    wire \sdrm_t_int/rcd_end ;
    wire \sdrm_t_int/G_65 ;
    wire \sdrm_t_int/brst_end ;
    wire \sdrm_t_int/cslt_end ;
    wire \sdrm_t_int/pre_ad_tri ;
    wire \sdrm_t_int/ki_end ;
    wire \sdrm_t_int/sdrm_st/state_0[12] ;
    wire \sdrm_t_int/sdrm_st/N_154 ;
    wire \sdrm_t_int/sdrm_st/N_153 ;
    wire \sdrm_t_int/auto_ref_out ;
    wire \sdrm_t_int/sdrm_st/state_h/N_148 ;
    wire \sdrm_t_int/sdrm_st/G_70 ;
    wire sys_int_int_ld_cnt_reg_3;
    wire \sys_int_int/ld_cnt_reg ;
    wire \sdrm_t_int/sdrm_st/state_h/G_38 ;
    wire \sdrm_t_int/sdrm_st/N_126 ;
    wire GLOBAL_LOGIC1;
    wire GLOBAL_LOGIC0;
    wire data_addr_n_reg;
    wire sd_ba_op;
    wire \sdrm_t_int/pre_locked ;
    wire GLOBAL_LOGIC1_0;
    wire GLOBAL_LOGIC1_1;
    wire GLOBAL_LOGIC1_2;
    wire GLOBAL_LOGIC1_3;
    wire GLOBAL_LOGIC1_4;
    wire GLOBAL_LOGIC1_5;
    wire GLOBAL_LOGIC1_6;
    wire GLOBAL_LOGIC1_7;
    wire GLOBAL_LOGIC1_8;
    wire GLOBAL_LOGIC1_9;
    wire GLOBAL_LOGIC1_10;
    wire GLOBAL_LOGIC1_11;
    wire GLOBAL_LOGIC1_12;
    wire GLOBAL_LOGIC1_13;
    wire GLOBAL_LOGIC1_14;
    wire GLOBAL_LOGIC1_15;
    wire GLOBAL_LOGIC1_16;
    wire GLOBAL_LOGIC1_17;
    wire GLOBAL_LOGIC1_18;
    wire GLOBAL_LOGIC1_19;
    wire GLOBAL_LOGIC1_20;
    wire GLOBAL_LOGIC1_21;
    wire GLOBAL_LOGIC1_22;
    wire GLOBAL_LOGIC1_23;
    wire GLOBAL_LOGIC1_24;
    wire GLOBAL_LOGIC1_25;
    wire GLOBAL_LOGIC1_26;
    wire GLOBAL_LOGIC1_27;
    wire GLOBAL_LOGIC1_28;
    wire GLOBAL_LOGIC1_29;
    wire GLOBAL_LOGIC1_30;
    wire GLOBAL_LOGIC1_31;
    wire GLOBAL_LOGIC1_32;
    wire GLOBAL_LOGIC1_33;
    wire GLOBAL_LOGIC1_34;
    wire GLOBAL_LOGIC1_35;
    wire GLOBAL_LOGIC1_36;
    wire GLOBAL_LOGIC1_37;
    wire GLOBAL_LOGIC1_38;
    wire GLOBAL_LOGIC1_39;
    wire GLOBAL_LOGIC1_40;
    wire GLOBAL_LOGIC1_41;
    wire GLOBAL_LOGIC1_42;
    wire GLOBAL_LOGIC1_43;
    wire GLOBAL_LOGIC1_44;
    wire GLOBAL_LOGIC1_45;
    wire GLOBAL_LOGIC1_46;
    wire GLOBAL_LOGIC1_47;
    wire GLOBAL_LOGIC1_48;
    wire GLOBAL_LOGIC1_49;
    wire GLOBAL_LOGIC1_50;
    wire GLOBAL_LOGIC1_51;
    wire GLOBAL_LOGIC1_52;
    wire GLOBAL_LOGIC1_53;
    wire GLOBAL_LOGIC1_54;
    wire GLOBAL_LOGIC0_0;
    wire GLOBAL_LOGIC0_1;
    wire GLOBAL_LOGIC0_2;
    wire GLOBAL_LOGIC0_3;
    wire GLOBAL_LOGIC0_4;
    wire GLOBAL_LOGIC0_5;
    wire GLOBAL_LOGIC0_6;
    wire GLOBAL_LOGIC0_7;
    wire GLOBAL_LOGIC0_8;
    wire GLOBAL_LOGIC0_9;
    wire GLOBAL_LOGIC0_10;
    wire GLOBAL_LOGIC0_11;
    wire GLOBAL_LOGIC0_12;
    wire GLOBAL_LOGIC0_13;
    wire GLOBAL_LOGIC0_14;
    wire GLOBAL_LOGIC0_15;
    wire GLOBAL_LOGIC0_16;
    wire GLOBAL_LOGIC0_17;
    wire GLOBAL_LOGIC0_18;
    wire GLOBAL_LOGIC0_19;
    wire GLOBAL_LOGIC0_20;
    wire GLOBAL_LOGIC0_21;
    wire GLOBAL_LOGIC0_22;
    wire GLOBAL_LOGIC0_23;
    wire GLOBAL_LOGIC0_24;
    wire GLOBAL_LOGIC0_25;
    wire GLOBAL_LOGIC0_26;
    wire GLOBAL_LOGIC0_27;
    wire GLOBAL_LOGIC0_28;
    wire GLOBAL_LOGIC0_29;
    wire GLOBAL_LOGIC0_30;
    wire GLOBAL_LOGIC0_31;
    wire GLOBAL_LOGIC0_32;
    wire GLOBAL_LOGIC0_33;
    wire GLOBAL_LOGIC0_34;
    wire GLOBAL_LOGIC0_35;
    wire GLOBAL_LOGIC0_36;
    wire GLOBAL_LOGIC0_37;
    wire GLOBAL_LOGIC0_38;
    wire GLOBAL_LOGIC0_39;
    wire GLOBAL_LOGIC0_40;
    wire GLOBAL_LOGIC0_41;
    wire GLOBAL_LOGIC0_42;
    wire GLOBAL_LOGIC0_43;
    wire GLOBAL_LOGIC0_44;
    wire GLOBAL_LOGIC0_45;
    wire GLOBAL_LOGIC0_46;
    wire GLOBAL_LOGIC0_47;
    wire GLOBAL_LOGIC0_48;
    wire GLOBAL_LOGIC0_49;
    wire \sd_data[10]/IBUF ;
    wire \sd_data[10]/OD ;
    wire \sd_data[10]/ENABLE ;
    wire \sd_data[10]/KEEPER ;
    wire \sd_data[10]/OUTBUF_GTS_AND ;
    wire \sd_data[11]/IBUF ;
    wire \sd_data[11]/OD ;
    wire \sd_data[11]/ENABLE ;
    wire \sd_data[11]/KEEPER ;
    wire \sd_data[11]/OUTBUF_GTS_AND ;
    wire \sd_dqm[0]/LOGIC_ZERO ;
    wire \sd_dqm[0]/KEEPER ;
    wire \Clk_SDp/OUTMUX ;
    wire \Clk_SDp/KEEPER ;
    wire \sd_data[20]/IBUF ;
    wire \sd_data[20]/OUTMUX ;
    wire \sd_data[20]/ENABLE ;
    wire \sd_data[20]/KEEPER ;
    wire \sd_data[20]/OUTBUF_GTS_AND ;
    wire \sd_data[12]/IBUF ;
    wire \sd_data[12]/OD ;
    wire \sd_data[12]/ENABLE ;
    wire \sd_data[12]/KEEPER ;
    wire \sd_data[12]/OUTBUF_GTS_AND ;
    wire \sd_dqm[1]/LOGIC_ZERO ;
    wire \sd_dqm[1]/KEEPER ;
    wire \sd_add[0]/OD ;
    wire \sd_add[0]/KEEPER ;
    wire \sd_data[21]/IBUF ;
    wire \sd_data[21]/OD ;
    wire \sd_data[21]/ENABLE ;
    wire \sd_data[21]/KEEPER ;
    wire \sd_data[21]/OUTBUF_GTS_AND ;
    wire \sd_data[13]/IBUF ;
    wire \sd_data[13]/OD ;
    wire \sd_data[13]/TORGTS ;
    wire \sd_data[13]/ENABLE ;
    wire \sd_data[13]/KEEPER ;
    wire \sd_data[13]/OUTBUF_GTS_AND ;
    wire \sd_dqm[2]/LOGIC_ZERO ;
    wire \sd_dqm[2]/KEEPER ;
    wire \sd_add[1]/OD ;
    wire \sd_add[1]/KEEPER ;
    wire \sd_we/OUTMUX ;
    wire \sd_we/KEEPER ;
    wire \sd_data[30]/IBUF ;
    wire \sd_data[30]/OUTMUX ;
    wire \sd_data[30]/ENABLE ;
    wire \sd_data[30]/KEEPER ;
    wire \sd_data[30]/OUTBUF_GTS_AND ;
    wire \sd_data[22]/IBUF ;
    wire \sd_data[22]/OUTMUX ;
    wire \sd_data[22]/ENABLE ;
    wire \sd_data[22]/KEEPER ;
    wire \sd_data[22]/OUTBUF_GTS_AND ;
    wire \sd_data[14]/IBUF ;
    wire \sd_data[14]/OUTMUX ;
    wire \sd_data[14]/ENABLE ;
    wire \sd_data[14]/KEEPER ;
    wire \sd_data[14]/OUTBUF_GTS_AND ;
    wire \sd_dqm[3]/LOGIC_ZERO ;
    wire \sd_dqm[3]/KEEPER ;
    wire \sd_add[2]/OUTMUX ;
    wire \sd_add[2]/KEEPER ;
    wire \sd_data[31]/IBUF ;
    wire \sd_data[31]/OUTMUX ;
    wire \sd_data[31]/ENABLE ;
    wire \sd_data[31]/KEEPER ;
    wire \sd_data[31]/OUTBUF_GTS_AND ;
    wire \sd_data[23]/IBUF ;
    wire \sd_data[23]/OD ;
    wire \sd_data[23]/ENABLE ;
    wire \sd_data[23]/KEEPER ;
    wire \sd_data[23]/OUTBUF_GTS_AND ;
    wire \sd_data[15]/IBUF ;
    wire \sd_data[15]/OUTMUX ;
    wire \sd_data[15]/ENABLE ;
    wire \sd_data[15]/KEEPER ;
    wire \sd_data[15]/OUTBUF_GTS_AND ;
    wire \sd_add[3]/OUTMUX ;
    wire \sd_add[3]/KEEPER ;
    wire \sd_data[16]/IBUF ;
    wire \sd_data[16]/OUTMUX ;
    wire \sd_data[16]/ENABLE ;
    wire \sd_data[16]/KEEPER ;
    wire \sd_data[16]/OUTBUF_GTS_AND ;
    wire \sd_data[24]/IBUF ;
    wire \sd_data[24]/OD ;
    wire \sd_data[24]/ENABLE ;
    wire \sd_data[24]/KEEPER ;
    wire \sd_data[24]/OUTBUF_GTS_AND ;
    wire \sd_add[4]/OD ;
    wire \sd_add[4]/KEEPER ;
    wire \sd_add[10]/OUTMUX ;
    wire \sd_add[10]/KEEPER ;
    wire \sd_data[17]/IBUF ;
    wire \sd_data[17]/OUTMUX ;
    wire \sd_data[17]/ENABLE ;
    wire \sd_data[17]/KEEPER ;
    wire \sd_data[17]/OUTBUF_GTS_AND ;