sdrm.par

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

Release v3.2.05i - Par D.24

Thu Nov  2 14:07:13 2000

par -w -ol 2 map.ncd sdrm.ncd sdrm.pcf


Constraints file: sdrm.pcf

Loading design for application par from file map.ncd.
   "sdrm" is an NCD, version 2.34, device xcv300, package bg432, speed -6
Loading device for application par from file 'v300.nph' in environment
/export/vol1/extra/tools/xilinx.
Device speed data version:  FINAL 1.111 2000-10-13.


Resolved that IOB <sd_data(10)> must be placed at site P2.
Resolved that IOB <sd_data(11)> must be placed at site P3.
Resolved that IOB <sd_dqm(0)> must be placed at site H1.
Resolved that IOB <Clk_SDp> must be placed at site AL17.
Resolved that IOB <sd_data(20)> must be placed at site Y4.
Resolved that IOB <sd_data(12)> must be placed at site N1.
Resolved that IOB <sd_dqm(1)> must be placed at site AF3.
Resolved that IOB <sd_add(0)> must be placed at site E1.
Resolved that IOB <sd_data(21)> must be placed at site Y3.
Resolved that IOB <sd_data(13)> must be placed at site N3.
Resolved that IOB <sd_dqm(2)> must be placed at site AG2.
Resolved that IOB <sd_add(1)> must be placed at site E2.
Resolved that IOB <sd_we> must be placed at site H2.
Resolved that IOB <sd_data(30)> must be placed at site R1.
Resolved that IOB <sd_data(22)> must be placed at site Y1.
Resolved that IOB <sd_data(14)> must be placed at site M1.
Resolved that IOB <sd_dqm(3)> must be placed at site AG1.
Resolved that IOB <sd_add(2)> must be placed at site E3.
Resolved that IOB <sd_data(31)> must be placed at site R2.
Resolved that IOB <sd_data(23)> must be placed at site W1.
Resolved that IOB <sd_data(15)> must be placed at site M2.
Resolved that GCLKIOB <Clk_FBp> must be placed at site AK16.
Resolved that IOB <sd_add(3)> must be placed at site D1.
Resolved that IOB <sd_data(16)> must be placed at site AB4.
Resolved that IOB <sd_data(24)> must be placed at site W3.
Resolved that IOB <sd_add(4)> must be placed at site E4.
Resolved that IOB <sd_add(10)> must be placed at site AD1.
Resolved that IOB <sd_data(17)> must be placed at site AA3.
Resolved that IOB <sd_data(25)> must be placed at site V2.
Resolved that IOB <sd_add(5)> must be placed at site AF2.
Resolved that IOB <we_rn> must be placed at site U29.
Resolved that IOB <sd_data(26)> must be placed at site V3.
Resolved that IOB <sd_data(18)> must be placed at site AA2.
Resolved that IOB <sd_add(6)> must be placed at site AD3.
Resolved that IOB <sd_data(27)> must be placed at site U1.
Resolved that IOB <sd_data(19)> must be placed at site Y2.
Resolved that IOB <sd_add(7)> must be placed at site AE2.
Resolved that IOB <sd_data(28)> must be placed at site U2.
Resolved that IOB <sd_add(8)> must be placed at site AD2.
Resolved that IOB <sd_cs1> must be placed at site F2.
Resolved that IOB <sd_data(29)> must be placed at site U3.
Resolved that IOB <sd_cs2> must be placed at site AJ6.
Resolved that IOB <sd_add(9)> must be placed at site AC3.
Resolved that GCLKIOB <Clkp> must be placed at site AL16.
Resolved that IOB <sd_ba> must be placed at site F3.
Resolved that IOB <AD(10)> must be placed at site K31.
Resolved that IOB <sd_data(0)> must be placed at site M3.
Resolved that IOB <AD(11)> must be placed at site L29.
Resolved that IOB <sd_data(1)> must be placed at site M4.
Resolved that IOB <AD(12)> must be placed at site L30.
Resolved that IOB <AD(20)> must be placed at site AD31.
Resolved that IOB <sd_data(2)> must be placed at site L2.
Resolved that IOB <AD(13)> must be placed at site M30.
Resolved that IOB <AD(21)> must be placed at site AD30.
Resolved that IOB <sd_data(3)> must be placed at site L3.
Resolved that IOB <AD(30)> must be placed at site R29.
Resolved that IOB <AD(14)> must be placed at site M29.
Resolved that IOB <AD(22)> must be placed at site AD28.
Resolved that IOB <sd_data(4)> must be placed at site K1.
Resolved that IOB <AD(31)> must be placed at site T31.
Resolved that IOB <AD(15)> must be placed at site M31.
Resolved that IOB <AD(23)> must be placed at site AE30.
Resolved that IOB <sd_data(5)> must be placed at site J2.
Resolved that IOB <AD(16)> must be placed at site AB29.
Resolved that IOB <AD(24)> must be placed at site N31.
Resolved that IOB <data_addr_n> must be placed at site U30.
Resolved that IOB <sd_data(6)> must be placed at site J3.
Resolved that IOB <AD(25)> must be placed at site N30.
Resolved that IOB <AD(17)> must be placed at site AC30.
Resolved that IOB <sd_data(7)> must be placed at site J4.
Resolved that IOB <AD(0)> must be placed at site W30.
Resolved that IOB <AD(18)> must be placed at site AC29.
Resolved that IOB <AD(26)> must be placed at site P30.
Resolved that IOB <sd_data(8)> must be placed at site R4.
Resolved that IOB <AD(1)> must be placed at site W29.
Resolved that IOB <AD(27)> must be placed at site P29.
Resolved that IOB <AD(19)> must be placed at site AC28.
Resolved that IOB <sd_data(9)> must be placed at site R3.
Resolved that IOB <AD(2)> must be placed at site Y31.
Resolved that IOB <AD(28)> must be placed at site R31.
Resolved that IOB <sd_ras> must be placed at site G2.
Resolved that IOB <AD(3)> must be placed at site Y30.
Resolved that IOB <AD(29)> must be placed at site R30.
Resolved that IOB <Reset> must be placed at site AJ4.
Resolved that IOB <AD(4)> must be placed at site Y29.
Resolved that IOB <sd_cas> must be placed at site H3.
Resolved that IOB <AD(5)> must be placed at site Y28.
Resolved that IOB <AD(6)> must be placed at site AA30.
Resolved that IOB <AD(7)> must be placed at site AB31.
Resolved that IOB <sd_cke> must be placed at site AC2.
Resolved that IOB <AD(8)> must be placed at site J30.
Resolved that IOB <AD(9)> must be placed at site K30.


Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            90 out of 316    28%

   Number of SLICEs                  258 out of 3072    8%

   Number of DLLs                      2 out of 4      50%
   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Timing Analysis.  REAL time: 6 secs 
Finished initial Timing Analysis.  REAL time: 16 secs 

Starting the placer. REAL time: 17 secs 
Placement pass 1 ..
Placer score = 93278
Placement pass 2 ..
Placer score = 87233
Optimizing ... 
Placer score = 80748
Improving the placement. REAL time: 19 secs 
Placer score = 81228
Placer score = 81331
Placer score = 81270
Placer score = 80790
Placer stage completed in real time: 21 secs 

All IOBs have been constrained to specific sites.
Placer completed in real time: 21 secs 

Dumping design to file sdrm.ncd.

Total REAL time to Placer completion: 23 secs 
Total CPU time to Placer completion: 21 secs 

0 connection(s) routed; 1298 unrouted active, 136 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 24 secs 
Starting iterative routing. 
Routing active signals.
.........
Improving timing.
End of iteration 1 
1434 successful; 0 unrouted; (0) REAL time: 1 mins 33 secs 
Constraints are met. 
Total REAL time: 1 mins 34 secs 
Total CPU  time: 1 mins 25 secs 
End of route.  1434 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

Total REAL time to Router completion: 1 mins 35 secs 
Total CPU time to Router completion: 1 mins 26 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 267


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.883 ns
   The Maximum Pin Delay is:                               5.898 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.965 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         494         472         224         131         113           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "clk" PERIOD =  16 nS   HIGH 50.000 % |            |            |      
--------------------------------------------------------------------------------
  PERIOD analysis for net "clk0c" derived f |            |            |      
  rom  NET "clk" PERIOD =  16 nS   HIGH 50. |            |            |      
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  PERIOD analysis for net "clk0b" derived f |            |            |      
  rom  NET "clk" PERIOD =  16 nS   HIGH 50. |            |            |      
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  PERIOD analysis for net "clk0a" derived f |            |            |      
  rom  NET "clk" PERIOD =  16 nS   HIGH 50. |            |            |      
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  NET "clk0c" PERIOD =  10 nS   HIGH 50.000 | 10.000ns   | 8.345ns    | 4    
   %                                        |            |            |      
--------------------------------------------------------------------------------
  NET "clk0b" PERIOD =  10 nS   HIGH 50.000 | 10.000ns   | 7.752ns    | 2    
   %                                        |            |            |      
--------------------------------------------------------------------------------
  NET "sdrm_t_int/locked_i" MAXDELAY = 6.50 | 6.500ns    | 5.273ns    |      
  0 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS10 = MAXDELAY FROM TIMEGRP "c2x" TO TIM | 8.000ns    | 4.199ns    | 2    
  EGRP "c1x" 8 nS                           |            |            |      
--------------------------------------------------------------------------------
  TS11 = MAXDELAY FROM TIMEGRP "c1x" TO TIM | 8.000ns    | 6.381ns    | 2    
  EGRP "c2x" 8 nS                           |            |            |      
--------------------------------------------------------------------------------
  COMP "sd_add(1)" OFFSET = OUT 2.500 nS  B | 2.500ns    | 3.601ns    | 2    
  EFORE COMP "Clkp"                         |            |            |      
--------------------------------------------------------------------------------
  COMP "sd_add(3)" OFFSET = OUT 2.500 nS  B | 2.500ns    | 4.534ns    | 2    
  EFORE COMP "Clkp"                         |            |            |      
--------------------------------------------------------------------------------
  COMP "sd_add(10)" OFFSET = OUT 2.500 nS   | 2.500ns    | 4.578ns    | 2    
  BEFORE COMP "Clkp"                        |            |            |      
--------------------------------------------------------------------------------
  COMP "sd_ba" OFFSET = OUT 2.500 nS  BEFOR | 2.500ns    | 3.977ns    | 2    
  E COMP "Clkp"                             |            |            |      
--------------------------------------------------------------------------------
  COMP "sd_add(7)" OFFSET = OUT 2.500 nS  B | 2.500ns    | 4.014ns    | 2    
  EFORE COMP "Clkp"                         |            |            |