sdrm.dly

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

Thu Nov  2 14:08:49 2000

File: sdrm.dly

 The 20 Worst Net Delays are:
-------------------------------
| Max Delay (ns)  | Netname   |
-------------------------------
   5.898            data_addr_n_reg
   5.273            sdrm_t_int/locked_i
   4.218            sd_add_op(2)
   4.099            ad_o(7)
   3.841            sd_add_op(3)
   3.833            sys_int_int/ld_cnt_reg
   3.805            ad_o(6)
   3.729            sd_doe_n(3)
   3.585            ad_o(9)
   3.431            we_rn_i
   3.352            sd_data_r(22)
   3.344            sd_cas_op
   3.330            ad_i(8)
   3.282            sd_add_op(8)
   3.268            ad_o(10)
   3.132            sd_data_r(1)
   3.112            ad_i(10)
   3.098            ad_tri
   3.089            ad_i(11)
   3.075            sdrm_t_int.sd_add_mx
---------------------------------

-------------------------------------------------------------------------------
                               Net Delays
-------------------------------------------------------------------------------

GLOBAL_LOGIC0
   ad_tri.X
         0.025  ad_tri.G4

GLOBAL_LOGIC0_0
   PWR_GND_0.Y
         0.659  ad_tri.G1
         0.524  ad_tri.G2

GLOBAL_LOGIC0_1
   PWR_GND_1.Y
         0.399  sd_data_reg(2).G3
         0.374  sd_data_reg(2).G4

GLOBAL_LOGIC0_10
   sd_data_reg(4).X
         0.025  sd_data_reg(4).G4

GLOBAL_LOGIC0_11
   sd_data_reg(3).X
         0.025  sd_data_reg(3).G4

GLOBAL_LOGIC0_12
   sdrm_t_int/locked_j.X
         0.025  sdrm_t_int/locked_j.G4

GLOBAL_LOGIC0_13
   sd_data_reg(11).X
         0.025  sd_data_reg(11).G4

GLOBAL_LOGIC0_14
   PWR_GND_4.Y
         0.387  sd_data_reg(3).G3

GLOBAL_LOGIC0_15
   PWR_GND_5.Y
         0.659  sdrm_t_int/locked_j.G1
         0.524  sdrm_t_int/locked_j.G2

GLOBAL_LOGIC0_16
   PWR_GND_6.Y
         0.387  sd_data_reg(17).G3

GLOBAL_LOGIC0_17
   PWR_VCC_19.Y
         0.387  sd_data_reg(11).G3

GLOBAL_LOGIC0_18
   PWR_GND_7.Y
         0.387  sd_data_reg(13).G3

GLOBAL_LOGIC0_19
   sd_data_reg(17).X
         0.025  sd_data_reg(17).G4

GLOBAL_LOGIC0_2
   PWR_VCC_4.Y
         0.387  sd_data_reg(25).G3

GLOBAL_LOGIC0_20
   PWR_GND_8.Y
         0.399  sd_data_reg(20).G3
         0.374  sd_data_reg(20).G4

GLOBAL_LOGIC0_21
   PWR_GND_9.Y
         0.399  sd_data_reg(24).G3
         0.374  sd_data_reg(24).G4

GLOBAL_LOGIC0_22
   sd_data_reg(13).X
         0.387  sd_data_reg(9).G3
         0.039  sd_data_reg(13).G4

GLOBAL_LOGIC0_23
   PWR_VCC_24.Y
         0.399  sd_data_reg(7).G3
         0.374  sd_data_reg(7).G4

GLOBAL_LOGIC0_24
   PWR_VCC_26.Y
         0.669  sd_data_reg(18).G3

GLOBAL_LOGIC0_25
   PWR_VCC_27.Y
         0.637  sd_data_reg(18).G4

GLOBAL_LOGIC0_26
   sd_data_reg(26).X
         0.025  sd_data_reg(26).G4

GLOBAL_LOGIC0_27
   sd_data_reg(9).X
         0.025  sd_data_reg(9).G4

GLOBAL_LOGIC0_28
   PWR_VCC_31.Y
         0.399  sd_data_reg(12).G3
         0.374  sd_data_reg(12).G4

GLOBAL_LOGIC0_29
   PWR_GND_10.Y
         0.399  sd_data_reg(21).G3
         0.374  sd_data_reg(21).G4

GLOBAL_LOGIC0_3
   PWR_GND_2.Y
         0.387  sd_data_reg(15).G3

GLOBAL_LOGIC0_30
   PWR_GND_11.Y
         0.387  sd_data_reg(26).G3

GLOBAL_LOGIC0_31
   PWR_GND_12.Y
         0.387  sd_data_reg(10).G3

GLOBAL_LOGIC0_32
   sd_data_reg(14).X
         0.025  sd_data_reg(14).G4

GLOBAL_LOGIC0_33
   sd_data_reg(29).X
         0.387  sd_data_reg(31).G3
         0.039  sd_data_reg(29).G4

GLOBAL_LOGIC0_34
   sd_data_r(21).X
         0.399  sd_data_reg(19).G3
         0.374  sd_data_reg(19).G4

GLOBAL_LOGIC0_35
   sd_data_reg(10).X
         0.025  sd_data_reg(10).G4

GLOBAL_LOGIC0_36
   PWR_GND_13.Y
         0.387  sd_data_reg(14).G3

GLOBAL_LOGIC0_37
   sd_data_reg(31).X
         0.039  sd_data_reg(31).G4
         0.387  sd_data_reg(29).G3

GLOBAL_LOGIC0_38
   PWR_GND_14.Y
         0.387  sd_data_reg(6).G3

GLOBAL_LOGIC0_39
   PWR_VCC_39.Y
         0.637  sd_data_reg(28).G4

GLOBAL_LOGIC0_4
   sd_data_reg(22).X
         0.025  sd_data_reg(22).G4

GLOBAL_LOGIC0_40
   sd_data_reg(6).X
         0.025  sd_data_reg(6).G4

GLOBAL_LOGIC0_41
   PWR_GND_15.Y
         0.399  sd_data_reg(1).G3
         0.374  sd_data_reg(1).G4

GLOBAL_LOGIC0_42
   PWR_GND_16.Y
         0.387  sd_data_reg(16).G3

GLOBAL_LOGIC0_43
   sd_data_reg(0).X
         0.698  sd_data_reg(0).G3
         0.053  sd_data_reg(0).G4
         0.656  sd_data_reg(28).G3

GLOBAL_LOGIC0_44
   sd_data_reg(30).X
         0.025  sd_data_reg(30).G4

GLOBAL_LOGIC0_45
   sd_data_reg(16).X
         0.025  sd_data_reg(16).G4

GLOBAL_LOGIC0_46
   PWR_GND_17.Y
         0.387  sd_data_reg(30).G3

GLOBAL_LOGIC0_47
   PWR_GND_18.Y
         0.399  sd_data_reg(5).G3
         0.374  sd_data_reg(5).G4

GLOBAL_LOGIC0_48
   PWR_GND_19.Y
         0.387  sd_data_reg(23).G3

GLOBAL_LOGIC0_49
   sd_data_reg(23).X
         0.025  sd_data_reg(23).G4

GLOBAL_LOGIC0_5
   sd_data_reg(25).X
         0.053  sd_data_reg(25).G4
         0.399  sd_data_reg(27).G3
         0.374  sd_data_reg(27).G4

GLOBAL_LOGIC0_6
   sd_data_reg(15).X
         0.039  sd_data_reg(15).G4
         0.387  sd_data_reg(8).G3

GLOBAL_LOGIC0_7
   PWR_GND_3.Y
         0.387  sd_data_reg(4).G3

GLOBAL_LOGIC0_8
   ref_max(9).X
         0.657  sd_data_reg(22).G3

GLOBAL_LOGIC0_9
   sd_data_reg(8).X
         0.025  sd_data_reg(8).G4

GLOBAL_LOGIC1
   PWR_VCC_0.X
         0.387  ad_tri.G3

GLOBAL_LOGIC1_0
   PWR_VCC_1.X
         0.512  sd_data_reg(2).G2

GLOBAL_LOGIC1_1
   PWR_VCC_2.X
         0.310  sd_data_reg(2).G1

GLOBAL_LOGIC1_10
   PWR_VCC_10.X
         0.524  sd_data_reg(25).G2
         0.524  sd_data_reg(11).G2

GLOBAL_LOGIC1_11
   PWR_VCC_11.X
         0.647  sd_data_reg(15).G1
         0.324  sd_data_reg(8).G1

GLOBAL_LOGIC1_12
   PWR_VCC_12.X
         0.310  sd_data_reg(4).G1

GLOBAL_LOGIC1_13
   PWR_VCC_13.X
         0.310  sd_data_reg(3).G1

GLOBAL_LOGIC1_14
   PWR_VCC_14.X
         0.512  sd_data_reg(20).G2

GLOBAL_LOGIC1_15
   PWR_VCC_15.X
         0.512  sd_data_reg(24).G2
         0.324  sd_data_reg(11).G1

GLOBAL_LOGIC1_16
   PWR_VCC_16.X
         0.512  sd_data_reg(8).G2

GLOBAL_LOGIC1_17
   PWR_VCC_17.X
         0.512  sd_data_reg(4).G2

GLOBAL_LOGIC1_18
   PWR_VCC_18.X
         0.310  sd_data_reg(20).G1

GLOBAL_LOGIC1_19
   PWR_VCC_19.X
         0.310  sd_data_reg(24).G1

GLOBAL_LOGIC1_2
   PWR_VCC_3.X
         0.523  sd_data_reg(27).G2

GLOBAL_LOGIC1_20
   PWR_VCC_20.X
         0.512  sd_data_reg(12).G2

GLOBAL_LOGIC1_21
   PWR_VCC_21.X
         0.310  sd_data_reg(17).G1

GLOBAL_LOGIC1_22
   PWR_VCC_22.X
         0.512  sd_data_reg(21).G2

GLOBAL_LOGIC1_23
   PWR_VCC_23.X
         0.512  sd_data_reg(26).G2

GLOBAL_LOGIC1_24
   sd_data_r(27).Y
         0.175  sd_data_reg(13).G2

GLOBAL_LOGIC1_25
   PWR_VCC_24.X
         0.310  sd_data_reg(12).G1

GLOBAL_LOGIC1_26
   PWR_VCC_25.X
         0.512  sd_data_reg(17).G2

GLOBAL_LOGIC1_27
   PWR_VCC_26.X
         0.324  sd_data_reg(18).G1
         0.512  sd_data_reg(19).G2

GLOBAL_LOGIC1_28
   PWR_VCC_27.X
         0.310  sd_data_reg(21).G1

GLOBAL_LOGIC1_29
   PWR_VCC_28.X
         0.310  sd_data_reg(26).G1

GLOBAL_LOGIC1_3
   PWR_VCC_4.X
         0.310  sd_data_reg(27).G1

GLOBAL_LOGIC1_30
   PWR_VCC_29.X
         0.512  sd_data_reg(14).G2

GLOBAL_LOGIC1_31
   PWR_VCC_30.X
         0.338  sd_data_reg(9).G1
         0.659  sd_data_reg(13).G1
         0.659  sd_data_reg(29).G1

GLOBAL_LOGIC1_32
   PWR_VCC_31.X
         0.310  sd_data_reg(7).G1

GLOBAL_LOGIC1_33
   PWR_VCC_32.X
         0.512  sd_data_reg(18).G2
         0.324  sd_data_reg(19).G1

GLOBAL_LOGIC1_34
   PWR_VCC_33.X
         0.310  sd_data_reg(14).G1

GLOBAL_LOGIC1_35
   sd_data_r(29).Y
         0.512  sd_data_reg(9).G2
         0.189  sd_data_reg(29).G2

GLOBAL_LOGIC1_36
   sd_data_r(31).Y
         0.512  sd_data_reg(7).G2

GLOBAL_LOGIC1_37
   PWR_VCC_34.X
         0.512  sd_data_reg(1).G2

GLOBAL_LOGIC1_38
   PWR_VCC_35.X
         0.310  sd_data_reg(10).G1

GLOBAL_LOGIC1_39
   PWR_VCC_36.X
         0.310  sd_data_reg(31).G1

GLOBAL_LOGIC1_4
   PWR_VCC_5.X
         0.922  sd_data_reg(22).G1

GLOBAL_LOGIC1_40
   PWR_VCC_37.X
         0.310  sd_data_reg(1).G1

GLOBAL_LOGIC1_41
   PWR_VCC_38.X
         0.512  sd_data_reg(10).G2

GLOBAL_LOGIC1_42
   PWR_VCC_39.X
         0.659  sd_data_reg(0).G1
         0.524  sd_data_reg(0).G2

GLOBAL_LOGIC1_43
   PWR_VCC_40.X
         0.512  sd_data_reg(31).G2

GLOBAL_LOGIC1_44
   PWR_VCC_41.X
         0.512  sd_data_reg(30).G2

GLOBAL_LOGIC1_45
   PWR_VCC_42.X
         0.310  sd_data_reg(6).G1

GLOBAL_LOGIC1_46
   PWR_VCC_43.X
         0.512  sd_data_reg(5).G2

GLOBAL_LOGIC1_47
   PWR_VCC_44.X
         0.310  sd_data_reg(30).G1

GLOBAL_LOGIC1_48
   PWR_VCC_45.X
         0.512  sd_data_reg(6).G2

GLOBAL_LOGIC1_49
   PWR_VCC_46.X
         0.310  sd_data_reg(5).G1

GLOBAL_LOGIC1_5
   PWR_VCC_6.X
         0.310  sd_data_reg(25).G1

GLOBAL_LOGIC1_50
   PWR_VCC_47.X
         0.310  sd_data_reg(16).G1

GLOBAL_LOGIC1_51
   PWR_VCC_48.X
         0.659  sd_data_reg(28).G1
         0.524  sd_data_reg(28).G2

GLOBAL_LOGIC1_52
   PWR_VCC_49.X
         0.512  sd_data_reg(16).G2

GLOBAL_LOGIC1_53
   PWR_VCC_50.X
         0.310  sd_data_reg(23).G1

GLOBAL_LOGIC1_54
   PWR_VCC_51.X
         0.512  sd_data_reg(23).G2

GLOBAL_LOGIC1_6
   sys_int_int/data_reg(31).Y
         0.175  sd_data_reg(15).G2

GLOBAL_LOGIC1_7
   PWR_VCC_7.X
         0.512  sd_data_reg(3).G2

GLOBAL_LOGIC1_8
   PWR_VCC_8.X
         0.387  sdrm_t_int/locked_j.G3

GLOBAL_LOGIC1_9
   PWR_VCC_9.X
         0.787  sd_data_reg(22).G2

act_st(0)
   act_st(1).YQ
         1.314  sdrm_t_int.sdrm_st.state(7).G1
         1.543  sdrm_t_int/sdrm_st/state_0(9).G2
         1.532  sys_int_int/ld_cnt_reg.F2
         1.570  sys_int_int/ld_cnt_reg.G2

act_st(1)
   act_st(1).XQ
         1.123  sdrm_t_int.sdrm_st.state(7).G2
         0.998  sdrm_t_int/sdrm_st/state_0(9).G3
         1.477  sys_int_int/ld_cnt_reg.F3
         1.457  sys_int_int/ld_cnt_reg.G3

act_st(2)
   act_st(2).YQ
         1.462  sdrm_t_int.sdrm_st.state(7).F3
         1.519  sdrm_t_int/sdrm_st/state_0(9).F4
         1.725  sdrm_t_int/sdrm_st/state_0(11).G3
         1.102  sdrm_t_int/sdrm_st/N_126.F3

ad_i(0)
   AD(0).I
         1.613  ad_reg(1).BY

ad_i(1)
   AD(1).I
         1.729  ad_reg(1).BX

ad_i(10)
   AD(10).I
         3.112  ad_reg(11).BY

ad_i(11)
   AD(11).I
         3.089  ad_reg(11).BX

ad_i(12)
   AD(12).I
         2.787  ad_reg(13).BY

ad_i(13)
   AD(13).I
         2.806  ad_reg(13).BX

ad_i(14)
   AD(14).I
         2.779  ad_reg(15).BY

ad_i(15)
   AD(15).I
         2.742  ad_reg(15).BX

ad_i(16)
   AD(16).I
         2.380  ad_reg(17).BY

ad_i(17)
   AD(17).I
         2.495  ad_reg(17).BX

ad_i(18)
   AD(18).I
         2.380  ad_reg(19).BY