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sd_ba | 6.023(R)|sd_cas | 6.245(R)|sd_data(0) | 5.448(R)|sd_data(1) | 5.615(R)|sd_data(10) | 6.391(R)|sd_data(11) | 6.457(R)|sd_data(12) | 5.909(R)|sd_data(13) | 5.991(R)|sd_data(14) | 5.816(R)|sd_data(15) | 5.660(R)|sd_data(16) | 5.383(R)|sd_data(17) | 5.485(R)|sd_data(18) | 6.380(R)|sd_data(19) | 6.456(R)|sd_data(2) | 6.240(R)|sd_data(20) | 5.661(R)|sd_data(21) | 6.086(R)|sd_data(22) | 5.658(R)|sd_data(23) | 5.975(R)|sd_data(24) | 5.969(R)|sd_data(25) | 5.796(R)|sd_data(26) | 5.982(R)|sd_data(27) | 5.612(R)|sd_data(28) | 5.536(R)|sd_data(29) | 5.652(R)|sd_data(3) | 5.869(R)|sd_data(30) | 5.105(R)|sd_data(31) | 5.105(R)|sd_data(4) | 5.670(R)|sd_data(5) | 6.353(R)|sd_data(6) | 5.904(R)|sd_data(7) | 6.112(R)|sd_data(8) | 5.441(R)|sd_data(9) | 5.576(R)|sd_ras | 5.948(R)|sd_we | 5.142(R)|---------------+------------+Clock to Setup on destination clock Clkp---------------+---------+---------+---------+---------+ | Src/Dest| Src/Dest| Src/Dest| Src/Dest|Source Clock |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|---------------+---------+---------+---------+---------+Clkp | 8.345| | | |---------------+---------+---------+---------+---------+Table of Timegroups:-------------------TimeGroup c2x:BELs: sdrm_t_int/I_AD_tri/SRL16E sdrm_t_int/brst_cntr_inst/count[0] sdrm_t_int/brst_cntr_inst/count[1] sdrm_t_int/brst_cntr_inst/count[2] sdrm_t_int/cslt_cntr_inst/count_sig[0] sdrm_t_int/cslt_cntr_inst/count_sig[1] sdrm_t_int/ki_cntr_inst/count_sig[0] sdrm_t_int/ki_cntr_inst/count_sig[1] sdrm_t_int/ki_cntr_inst/count_sig[2] sdrm_t_int/ki_cntr_inst/count_sig[3] sdrm_t_int/rcd_cntr_inst/count_sig[0] sdrm_t_int/rcd_cntr_inst/count_sig[1] sdrm_t_int/sdrm_st/state_h/state[0] sdrm_t_int/sdrm_st/state_h/state[1] sdrm_t_int/sdrm_st/state_h/state[2] sdrm_t_int/sdrm_st/state_h/state[3] sdrm_t_int/sdrm_st/state_h/state[4] sdrm_t_int/sdrm_st/state_h/state[5] sdrm_t_int/sdrm_st/state_h/state[6] sdrm_t_int/sdrm_st/state_h/state[7] sdrm_t_int/sdrm_st/state_h/state[8] sdrm_t_int/sdrm_st/state_h/state[9] sdrm_t_int/sdrm_st/state_h/state[10] sdrm_t_int/sdrm_st/state_h/state[11] sdrm_t_int/sdrm_st/state_h/state[12] sdrm_t_int/Locked_i sdrm_t_int/clr_ref_d sdrm_t_int/ld_brst sdrm_t_int/ld_cslt sdrm_t_int/ld_rcd sdrm_t_int/sd_add_mx sdrm_t_int/sd_add_o[0] sdrm_t_int/sd_add_o[1] sdrm_t_int/sd_add_o[2] sdrm_t_int/sd_add_o[3] sdrm_t_int/sd_add_o[4] sdrm_t_int/sd_add_o[5] sdrm_t_int/sd_add_o[6] sdrm_t_int/sd_add_o[7] sdrm_t_int/sd_add_o[8] sdrm_t_int/sd_add_o[9] sdrm_t_int/sd_add_o[10] sdrm_t_int/sd_ba_o sdrm_t_int/sd_cas_o sdrm_t_int/sd_doe_n[3] sdrm_t_int/sd_ras_o sdrm_t_int/sd_we_o sys_int_int/SRL16_0/SRL16E sys_int_int/SRL16_1/SRL16E sys_int_int/SRL16_2/SRL16E sys_int_int/SRL16_3/SRL16E sys_int_int/SRL16_4/SRL16E sys_int_int/SRL16_5/SRL16E sys_int_int/SRL16_6/SRL16E sys_int_int/SRL16_7/SRL16E sys_int_int/SRL16_8/SRL16E sys_int_int/SRL16_9/SRL16E sys_int_int/SRL16_10/SRL16E sys_int_int/SRL16_11/SRL16E sys_int_int/SRL16_12/SRL16E sys_int_int/SRL16_13/SRL16E sys_int_int/SRL16_14/SRL16E sys_int_int/SRL16_15/SRL16E sys_int_int/SRL16_16/SRL16E sys_int_int/SRL16_17/SRL16E sys_int_int/SRL16_18/SRL16E sys_int_int/SRL16_19/SRL16E sys_int_int/SRL16_20/SRL16E sys_int_int/SRL16_21/SRL16E sys_int_int/SRL16_22/SRL16E sys_int_int/SRL16_23/SRL16E sys_int_int/SRL16_24/SRL16E sys_int_int/SRL16_25/SRL16E sys_int_int/SRL16_26/SRL16E sys_int_int/SRL16_27/SRL16E sys_int_int/SRL16_28/SRL16E sys_int_int/SRL16_29/SRL16E sys_int_int/SRL16_30/SRL16E sys_int_int/SRL16_31/SRL16E sys_int_int/Act_st[0] sys_int_int/Act_st[1] sys_int_int/Act_st[2] sys_int_int/Add_reg[2] sys_int_int/Add_reg[3] sys_int_int/Add_reg[4] sys_int_int/Add_reg[5] sys_int_int/Add_reg[6] sys_int_int/Add_reg[7] sys_int_int/Add_reg[8] sys_int_int/Add_reg[9] sys_int_int/Add_reg[10] sys_int_int/Add_reg[11] sys_int_int/Add_reg[12] sys_int_int/Add_reg[13] sys_int_int/Add_reg[14] sys_int_int/Add_reg[15] sys_int_int/Add_reg[16] sys_int_int/Add_reg[17] sys_int_int/Add_reg[18] sys_int_int/Add_reg[19] sys_int_int/Add_reg[20] sys_int_int/Add_reg[21] sys_int_int/cntrl[0] sys_int_int/cntrl[1] sys_int_int/cntrl[2] sys_int_int/cntrl[3] sys_int_int/cntrl[4] sys_int_int/cntrl[5] sys_int_int/cntrl[6] sys_int_int/cntrl[8] sys_int_int/cntrl[9] sys_int_int/cntrl[10] sys_int_int/cntrl[11] sys_int_int/cntrl[12] sys_int_int/cntrl[13] sys_int_int/cntrl[14] sys_int_int/cntrl[15] sys_int_int/cntrl[16] sys_int_int/cntrl[17] sys_int_int/cntrl[18] sys_int_int/cntrl[19] sys_int_int/cntrl[20] sys_int_int/cntrl[21] sys_int_int/cntrl[22] sys_int_int/cntrl[23] sys_int_int/cntrl[24] sys_int_int/cntrl[25] sys_int_int/cntrl[26] sys_int_int/cntrl[27] sys_int_int/data_reg[0] sys_int_int/data_reg[1] sys_int_int/data_reg[2] sys_int_int/data_reg[3] sys_int_int/data_reg[4] sys_int_int/data_reg[5] sys_int_int/data_reg[6] sys_int_int/data_reg[7] sys_int_int/data_reg[8] sys_int_int/data_reg[9] sys_int_int/data_reg[10] sys_int_int/data_reg[11] sys_int_int/data_reg[12] sys_int_int/data_reg[13] sys_int_int/data_reg[14] sys_int_int/data_reg[15] sys_int_int/data_reg[16] sys_int_int/data_reg[17] sys_int_int/data_reg[18] sys_int_int/data_reg[19] sys_int_int/data_reg[20] sys_int_int/data_reg[21] sys_int_int/data_reg[22] sys_int_int/data_reg[23] sys_int_int/data_reg[24] sys_int_int/data_reg[25] sys_int_int/data_reg[26] sys_int_int/data_reg[27] sys_int_int/data_reg[28] sys_int_int/data_reg[29] sys_int_int/data_reg[30] sys_int_int/data_reg[31] sys_int_int/ld_cnt_reg ad_o[0] ad_o[1] ad_o[2] ad_o[3] ad_o[4] ad_o[5] ad_o[6] ad_o[7] ad_o[8] ad_o[9] ad_o[10] ad_o[11] ad_o[12] ad_o[13] ad_o[14] ad_o[15] ad_o[16] ad_o[17] ad_o[18] ad_o[19] ad_o[20] ad_o[21] ad_o[22] ad_o[23] ad_o[24] ad_o[25] ad_o[26] ad_o[27] ad_o[28] ad_o[29] ad_o[30] ad_o[31] ad_reg[0] ad_reg[1] ad_reg[2] ad_reg[3] ad_reg[4] ad_reg[5] ad_reg[6] ad_reg[7] ad_reg[8] ad_reg[9] ad_reg[10] ad_reg[11] ad_reg[12] ad_reg[13] ad_reg[14] ad_reg[15] ad_reg[16] ad_reg[17] ad_reg[18] ad_reg[19] ad_reg[20] ad_reg[21] ad_reg[22] ad_reg[23] ad_reg[24] ad_reg[25] ad_reg[26] ad_reg[27] ad_reg[28] ad_reg[29] ad_reg[30] ad_reg[31] data_addr_n_reg sd_add_o[0] sd_add_o[1] sd_add_o[2] sd_add_o[3] sd_add_o[4] sd_add_o[5] sd_add_o[6] sd_add_o[7] sd_add_o[8] sd_add_o[9] sd_add_o[10] sd_ba_o sd_cas_o sd_data_o[0] sd_data_o[1] sd_data_o[2] sd_data_o[3] sd_data_o[4] sd_data_o[5] sd_data_o[6] sd_data_o[7] sd_data_o[8] sd_data_o[9] sd_data_o[10] sd_data_o[11] sd_data_o[12] sd_data_o[13] sd_data_o[14] sd_data_o[15] sd_data_o[16] sd_data_o[17] sd_data_o[18] sd_data_o[19] sd_data_o[20] sd_data_o[21] sd_data_o[22] sd_data_o[23] sd_data_o[24] sd_data_o[25] sd_data_o[26] sd_data_o[27] sd_data_o[28] sd_data_o[29] sd_data_o[30] sd_data_o[31] sd_data_r[0] sd_data_r[1] sd_data_r[2] sd_data_r[3] sd_data_r[4] sd_data_r[5] sd_data_r[6] sd_data_r[7] sd_data_r[8] sd_data_r[9] sd_data_r[10] sd_data_r[11] sd_data_r[12] sd_data_r[13] sd_data_r[14] sd_data_r[15] sd_data_r[16] sd_data_r[17] sd_data_r[18] sd_data_r[19] sd_data_r[20] sd_data_r[21] sd_data_r[22] sd_data_r[23] sd_data_r[24] sd_data_r[25] sd_data_r[26] sd_data_r[27] sd_data_r[28] sd_data_r[29] sd_data_r[30] sd_data_r[31] sd_data_t[31] sd_data_t_rep0[31] sd_data_t_rep1[31] sd_data_t_rep2[31] sd_data_t_rep3[31] sd_data_t_rep4[31] sd_data_t_rep5[31] sd_data_t_rep6[31] sd_data_t_rep7[31] sd_data_t_rep8[31] sd_data_t_rep9[31] sd_data_t_rep10[31] sd_data_t_rep11[31] sd_data_t_rep12[31] sd_data_t_rep13[31] sd_data_t_rep14[31] sd_data_t_rep15[31] sd_data_t_rep16[31] sd_data_t_rep17[31] sd_data_t_rep18[31] sd_data_t_rep19[31] sd_data_t_rep20[31] sd_data_t_rep21[31] sd_data_t_rep22[31] sd_data_t_rep23[31] sd_data_t_rep24[31] sd_data_t_rep25[31] sd_data_t_rep26[31] sd_data_t_rep27[31] sd_data_t_rep28[31] sd_data_t_rep29[31] sd_data_t_rep30[31] sd_doe_n[0] sd_ras_o sd_we_o TimeGroup c1x:BELs: sdrm_t_int/SRL16_inst/SRL16E sdrm_t_int/ref_cntr_inst/auto_ref sdrm_t_int/ref_cntr_inst/rcount[0] sdrm_t_int/ref_cntr_inst/rcount[1] sdrm_t_int/ref_cntr_inst/rcount[2] sdrm_t_int/ref_cntr_inst/rcount[3] sdrm_t_int/ref_cntr_inst/rcount[4] sdrm_t_int/ref_cntr_inst/rcount[5] sdrm_t_int/ref_cntr_inst/rcount[6] sdrm_t_int/ref_cntr_inst/rcount[7] sdrm_t_int/ref_cntr_inst/rcount[8] sdrm_t_int/ref_cntr_inst/rcount[9] sdrm_t_int/ref_cntr_inst/rcount[10] sdrm_t_int/ref_cntr_inst/rcount[11] sdrm_t_int/ref_cntr_inst/rcount[12] sdrm_t_int/ref_cntr_inst/rcount[13] sdrm_t_int/ref_cntr_inst/rcount[14] sdrm_t_int/ref_cntr_inst/rcount[15] TimeGroup TWDLLS:Comps: dll0 dll1 Timing summary:---------------Timing errors: 0 Score: 0Constraints cover 1200 paths, 1 nets, and 1129 connections (87.0% coverage)Design statistics: Minimum period: 8.345ns (Maximum frequency: 119.832MHz) Maximum path delay from/to any node: 6.381ns Maximum net delay: 5.273ns Maximum input arrival time after clock: 7.478ns Maximum output required time before clock: 4.895nsAnalysis completed Thu Nov 2 14:09:11 2000--------------------------------------------------------------------------------⌨️ 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