sdrm.twr

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

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Xilinx TRACE, Version D.24
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

trce sdrm.ncd sdrm.pcf -e 3 -o sdrm.twr

Design file:              sdrm.ncd
Physical constraint file: sdrm.pcf
Device,speed:             xcv300,-6 (FINAL 1.111 2000-10-13)
Report level:             error report
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Timing constraint: NET "clk" PERIOD =  16 nS   HIGH 50.000 % ;
 0 items analyzed, 0 timing errors detected.
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Timing constraint: PERIOD analysis for net "clk0c" derived from
 NET "clk" PERIOD =  16 nS   HIGH 50.000 % ;
 duty cycle corrected to 16 nS  HIGH 8 nS 
 0 items analyzed, 0 timing errors detected.
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Timing constraint: PERIOD analysis for net "clk0b" derived from
 NET "clk" PERIOD =  16 nS   HIGH 50.000 % ;
 divided by 2.00 and duty cycle corrected to 8 nS  HIGH 4 nS 
 0 items analyzed, 0 timing errors detected.
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Timing constraint: PERIOD analysis for net "clk0a" derived from
 NET "clk" PERIOD =  16 nS   HIGH 50.000 % ;
 divided by 2.00 and duty cycle corrected to 8 nS  HIGH 4 nS 
 0 items analyzed, 0 timing errors detected.
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Timing constraint: NET "clk0c" PERIOD =  10 nS   HIGH 50.000 % ;
 408 items analyzed, 0 timing errors detected.
 Minimum period is   8.345ns.
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Timing constraint: NET "clk0b" PERIOD =  10 nS   HIGH 50.000 % ;
 662 items analyzed, 0 timing errors detected.
 Minimum period is   7.752ns.
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Timing constraint: NET "sdrm_t_int/locked_i" MAXDELAY = 6.500 nS  ;
 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   5.273ns.
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Timing constraint: TS10 = MAXDELAY FROM TIMEGRP "c2x" TO TIMEGRP "c1x" 8 nS  ; 
 16 items analyzed, 0 timing errors detected.
 Maximum delay is   4.199ns.
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Timing constraint: TS11 = MAXDELAY FROM TIMEGRP "c1x" TO TIMEGRP "c2x" 8 nS  ; 
 3 items analyzed, 0 timing errors detected.
 Maximum delay is   6.381ns.
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Timing constraint: COMP "sd_add(1)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.601ns.
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Timing constraint: COMP "sd_add(3)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.534ns.
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Timing constraint: COMP "sd_add(10)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.578ns.
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Timing constraint: COMP "sd_ba" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.977ns.
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Timing constraint: COMP "sd_add(7)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.014ns.
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Timing constraint: COMP "sd_add(0)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.411ns.
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Timing constraint: COMP "sd_we" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.858ns.
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Timing constraint: COMP "sd_add(2)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.545ns.
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Timing constraint: COMP "sd_add(4)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.592ns.
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Timing constraint: COMP "sd_cas" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.755ns.
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Timing constraint: COMP "sd_add(9)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.512ns.
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Timing constraint: COMP "sd_ras" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.052ns.
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Timing constraint: COMP "sd_add(5)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.915ns.
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Timing constraint: COMP "sd_add(8)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.435ns.
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Timing constraint: COMP "sd_add(6)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.883ns.
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Timing constraint: COMP "sd_data(4)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 2 items analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.330ns.
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Timing constraint: COMP "sd_data(4)" OFFSET = IN 6.300 nS  AFTER COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   7.036ns.
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Timing constraint: COMP "sd_data(5)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 2 items analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.647ns.
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Timing constraint: COMP "sd_data(5)" OFFSET = IN 6.300 nS  AFTER COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   6.744ns.
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Timing constraint: COMP "sd_data(6)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 2 items analyzed, 0 timing errors detected.
 Maximum allowable offset is   4.096ns.
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Timing constraint: COMP "sd_data(6)" OFFSET = IN 6.300 nS  AFTER COMP "Clkp" ;
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is   6.874ns.
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Timing constraint: COMP "sd_data(10)" OFFSET = OUT 2.500 nS  BEFORE COMP "Clkp" ;
 2 items analyzed, 0 timing errors detected.
 Maximum allowable offset is   3.609ns.
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