map.mrp

The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode

Xilinx Mapping Report File for Design 'sdrm'
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

Design Information
------------------
Command Line   : map -p xcv300-6-bg432 -o map.ncd sdrm.ngd sdrm.pcf 
Target Device  : xv300
Target Package : bg432
Target Speed   : -6
Mapper Version : virtex -- D.24
Mapped Date    : Thu Nov  2 14:07:03 2000

Design Summary
--------------
   Number of errors:      0
   Number of warnings:    1
   Number of Slices:                258 out of  3,072    8%
   Number of Slices containing
      unrelated logic:                0 out of    258    0%
   Number of Slice Flip Flops:      323 out of  6,144    5%
   Total Number 4 input LUTs:       164 out of  6,144    2%
      Number used as LUTs:                        130
      Number used as Shift registers:              34
   Number of bonded IOBs:            90 out of    316   28%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    2 out of      4   50%
Total equivalent gate count for design:  22,034
Additional JTAG gate count for IOBs:  4,416

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Design Attributes
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - Added Logic
Section 7 - Expanded Logic
Section 8 - Signal Cross-Reference
Section 9 - Symbol Cross-Reference
Section 10 - IOB Properties
Section 11 - RPMs
Section 12 - Guide Report
Section 13 - Area Group Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:MapLib:159 - Net Timing constraints on signal Clkp are pushed forward
   through input buffer.

Section 3 - Design Attributes
-----------------------------
 Attribute LOC
   "E2" for signal(s) sd_add(1) on symbol "sd_add(1).PAD"
   "D1" for signal(s) sd_add(3) on symbol "sd_add(3).PAD"
   "AD1" for signal(s) sd_add(10) on symbol "sd_add(10).PAD"
   "F3" for signal(s) sd_ba on symbol "sd_ba.PAD"
   "AE2" for signal(s) sd_add(7) on symbol "sd_add(7).PAD"
   "E1" for signal(s) sd_add(0) on symbol "sd_add(0).PAD"
   "H2" for signal(s) sd_we on symbol "sd_we.PAD"
   "E3" for signal(s) sd_add(2) on symbol "sd_add(2).PAD"
   "E4" for signal(s) sd_add(4) on symbol "sd_add(4).PAD"
   "H3" for signal(s) sd_cas on symbol "sd_cas.PAD"
   "AC3" for signal(s) sd_add(9) on symbol "sd_add(9).PAD"
   "G2" for signal(s) sd_ras on symbol "sd_ras.PAD"
   "AF2" for signal(s) sd_add(5) on symbol "sd_add(5).PAD"
   "AD2" for signal(s) sd_add(8) on symbol "sd_add(8).PAD"
   "AD3" for signal(s) sd_add(6) on symbol "sd_add(6).PAD"
   "AE30" for signal(s) AD(23) on symbol "AD(23).PAD"
   "AC30" for signal(s) AD(17) on symbol "AD(17).PAD"
   "R31" for signal(s) AD(28) on symbol "AD(28).PAD"
   "AC28" for signal(s) AD(19) on symbol "AD(19).PAD"
   "M31" for signal(s) AD(15) on symbol "AD(15).PAD"
   "N31" for signal(s) AD(24) on symbol "AD(24).PAD"
   "AB29" for signal(s) AD(16) on symbol "AD(16).PAD"
   "K1" for signal(s) sd_data(4) on symbol "sd_data(4).PAD"
   "J2" for signal(s) sd_data(5) on symbol "sd_data(5).PAD"
   "J3" for signal(s) sd_data(6) on symbol "sd_data(6).PAD"
   "AD31" for signal(s) AD(20) on symbol "AD(20).PAD"
   "AD30" for signal(s) AD(21) on symbol "AD(21).PAD"
   "AD28" for signal(s) AD(22) on symbol "AD(22).PAD"
   "P2" for signal(s) sd_data(10) on symbol "sd_data(10).PAD"
   "P3" for signal(s) sd_data(11) on symbol "sd_data(11).PAD"
   "P30" for signal(s) AD(26) on symbol "AD(26).PAD"
   "P29" for signal(s) AD(27) on symbol "AD(27).PAD"
   "M1" for signal(s) sd_data(14) on symbol "sd_data(14).PAD"
   "M29" for signal(s) AD(14) on symbol "AD(14).PAD"
   "M4" for signal(s) sd_data(1) on symbol "sd_data(1).PAD"
   "L2" for signal(s) sd_data(2) on symbol "sd_data(2).PAD"
   "AA2" for signal(s) sd_data(18) on symbol "sd_data(18).PAD"
   "W29" for signal(s) AD(1) on symbol "AD(1).PAD"
   "Y31" for signal(s) AD(2) on symbol "AD(2).PAD"
   "Y30" for signal(s) AD(3) on symbol "AD(3).PAD"
   "Y29" for signal(s) AD(4) on symbol "AD(4).PAD"
   "Y28" for signal(s) AD(5) on symbol "AD(5).PAD"
   "AA30" for signal(s) AD(6) on symbol "AD(6).PAD"
   "AB31" for signal(s) AD(7) on symbol "AD(7).PAD"
   "J30" for signal(s) AD(8) on symbol "AD(8).PAD"
   "N1" for signal(s) sd_data(12) on symbol "sd_data(12).PAD"
   "N3" for signal(s) sd_data(13) on symbol "sd_data(13).PAD"
   "L29" for signal(s) AD(11) on symbol "AD(11).PAD"
   "M2" for signal(s) sd_data(15) on symbol "sd_data(15).PAD"
   "M30" for signal(s) AD(13) on symbol "AD(13).PAD"
   "L3" for signal(s) sd_data(3) on symbol "sd_data(3).PAD"
   "AC29" for signal(s) AD(18) on symbol "AD(18).PAD"
   "J4" for signal(s) sd_data(7) on symbol "sd_data(7).PAD"
   "R4" for signal(s) sd_data(8) on symbol "sd_data(8).PAD"
   "R3" for signal(s) sd_data(9) on symbol "sd_data(9).PAD"
   "N30" for signal(s) AD(25) on symbol "AD(25).PAD"
   "R30" for signal(s) AD(29) on symbol "AD(29).PAD"
   "R29" for signal(s) AD(30) on symbol "AD(30).PAD"
   "T31" for signal(s) AD(31) on symbol "AD(31).PAD"
   "Y4" for signal(s) sd_data(20) on symbol "sd_data(20).PAD"
   "Y3" for signal(s) sd_data(21) on symbol "sd_data(21).PAD"
   "Y1" for signal(s) sd_data(22) on symbol "sd_data(22).PAD"
   "W1" for signal(s) sd_data(23) on symbol "sd_data(23).PAD"
   "W3" for signal(s) sd_data(24) on symbol "sd_data(24).PAD"
   "V2" for signal(s) sd_data(25) on symbol "sd_data(25).PAD"
   "V3" for signal(s) sd_data(26) on symbol "sd_data(26).PAD"
   "K30" for signal(s) AD(9) on symbol "AD(9).PAD"
   "K31" for signal(s) AD(10) on symbol "AD(10).PAD"
   "U3" for signal(s) sd_data(29) on symbol "sd_data(29).PAD"
   "L30" for signal(s) AD(12) on symbol "AD(12).PAD"
   "M3" for signal(s) sd_data(0) on symbol "sd_data(0).PAD"
   "AA3" for signal(s) sd_data(17) on symbol "sd_data(17).PAD"
   "Y2" for signal(s) sd_data(19) on symbol "sd_data(19).PAD"
   "W30" for signal(s) AD(0) on symbol "AD(0).PAD"
   "U1" for signal(s) sd_data(27) on symbol "sd_data(27).PAD"
   "U2" for signal(s) sd_data(28) on symbol "sd_data(28).PAD"
   "R1" for signal(s) sd_data(30) on symbol "sd_data(30).PAD"
   "R2" for signal(s) sd_data(31) on symbol "sd_data(31).PAD"
   "AB4" for signal(s) sd_data(16) on symbol "sd_data(16).PAD"
   "U29" on symbol "we_rn.PAD"
   "AL17" for signal(s) Clk_SDp on symbol "Clk_SDp.PAD"
   "U30" on symbol "data_addr_n.PAD"
   "AJ4" on symbol "Reset.PAD"
   "AL16" on symbol "Clkp.PAD"
   "AK16" on symbol "Clk_FBp.PAD"
   "AJ6" for signal(s) sd_cs2 on symbol "sd_cs2.PAD"
   "H1" for signal(s) sd_dqm(0) on symbol "sd_dqm(0).PAD"
   "AF3" for signal(s) sd_dqm(1) on symbol "sd_dqm(1).PAD"
   "AG2" for signal(s) sd_dqm(2) on symbol "sd_dqm(2).PAD"
   "AG1" for signal(s) sd_dqm(3) on symbol "sd_dqm(3).PAD"
   "AC2" for signal(s) sd_cke on symbol "sd_cke.PAD"
   "F2" for signal(s) sd_cs1 on symbol "sd_cs1.PAD"

Section 4 - Removed Logic Summary
---------------------------------
  44 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		GND
VCC 		VCC
GND 		sdrm_t_int/GND
X_ONE 		sdrm_t_int/I_AD_tri/VCC
X_ONE 		sdrm_t_int/SRL16_inst/VCC
VCC 		sdrm_t_int/VCC
VCC 		sdrm_t_int/brst_cntr_inst/VCC
VCC 		sdrm_t_int/ki_cntr_inst/VCC
GND 		sdrm_t_int/ref_cntr_inst/GND
VCC 		sdrm_t_int/ref_cntr_inst/VCC
GND 		sys_int_int/GND
X_ONE 		sys_int_int/SRL16_0/VCC
X_ONE 		sys_int_int/SRL16_1/VCC
X_ONE 		sys_int_int/SRL16_10/VCC
X_ONE 		sys_int_int/SRL16_11/VCC
X_ONE 		sys_int_int/SRL16_12/VCC
X_ONE 		sys_int_int/SRL16_13/VCC
X_ONE 		sys_int_int/SRL16_14/VCC
X_ONE 		sys_int_int/SRL16_15/VCC
X_ONE 		sys_int_int/SRL16_16/VCC
X_ONE 		sys_int_int/SRL16_17/VCC
X_ONE 		sys_int_int/SRL16_18/VCC
X_ONE 		sys_int_int/SRL16_19/VCC
X_ONE 		sys_int_int/SRL16_2/VCC
X_ONE 		sys_int_int/SRL16_20/VCC
X_ONE 		sys_int_int/SRL16_21/VCC
X_ONE 		sys_int_int/SRL16_22/VCC
X_ONE 		sys_int_int/SRL16_23/VCC
X_ONE 		sys_int_int/SRL16_24/VCC
X_ONE 		sys_int_int/SRL16_25/VCC
X_ONE 		sys_int_int/SRL16_26/VCC
X_ONE 		sys_int_int/SRL16_27/VCC
X_ONE 		sys_int_int/SRL16_28/VCC
X_ONE 		sys_int_int/SRL16_29/VCC
X_ONE 		sys_int_int/SRL16_3/VCC
X_ONE 		sys_int_int/SRL16_30/VCC
X_ONE 		sys_int_int/SRL16_31/VCC
X_ONE 		sys_int_int/SRL16_4/VCC
X_ONE 		sys_int_int/SRL16_5/VCC
X_ONE 		sys_int_int/SRL16_6/VCC
X_ONE 		sys_int_int/SRL16_7/VCC
X_ONE 		sys_int_int/SRL16_8/VCC
X_ONE 		sys_int_int/SRL16_9/VCC
VCC 		sys_int_int/VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - Added Logic
-----------------------

Section 7 - Expanded Logic
--------------------------
To enable this section, set the detailed map report option and rerun map.

Section 8 - Signal Cross-Reference
----------------------------------
To enable this section, set the detailed map report option and rerun map.

Section 9 - Symbol Cross-Reference
----------------------------------
To enable this section, set the detailed map report option and rerun map.

Section 10 - IOB Properties
---------------------------
Clk_FBp (GCLKIOB)
Clkp (GCLKIOB)
AD(0) (IOB) : SLEW=FAST DRIVE=12
AD(1) (IOB) : SLEW=FAST DRIVE=12
AD(10) (IOB) : SLEW=FAST DRIVE=12
AD(11) (IOB) : SLEW=FAST DRIVE=12
AD(12) (IOB) : SLEW=FAST DRIVE=12
AD(13) (IOB) : SLEW=FAST DRIVE=12
AD(14) (IOB) : SLEW=FAST DRIVE=12
AD(15) (IOB) : SLEW=FAST DRIVE=12
AD(16) (IOB) : SLEW=FAST DRIVE=12
AD(17) (IOB) : SLEW=FAST DRIVE=12
AD(18) (IOB) : SLEW=FAST DRIVE=12
AD(19) (IOB) : SLEW=FAST DRIVE=12
AD(2) (IOB) : SLEW=FAST DRIVE=12
AD(20) (IOB) : SLEW=FAST DRIVE=12
AD(21) (IOB) : SLEW=FAST DRIVE=12
AD(22) (IOB) : SLEW=FAST DRIVE=12
AD(23) (IOB) : SLEW=FAST DRIVE=12
AD(24) (IOB) : SLEW=FAST DRIVE=12
AD(25) (IOB) : SLEW=FAST DRIVE=12
AD(26) (IOB) : SLEW=FAST DRIVE=12
AD(27) (IOB) : SLEW=FAST DRIVE=12
AD(28) (IOB) : SLEW=FAST DRIVE=12
AD(29) (IOB) : SLEW=FAST DRIVE=12
AD(3) (IOB) : SLEW=FAST DRIVE=12
AD(30) (IOB) : SLEW=FAST DRIVE=12
AD(31) (IOB) : SLEW=FAST DRIVE=12
AD(4) (IOB) : SLEW=FAST DRIVE=12
AD(5) (IOB) : SLEW=FAST DRIVE=12
AD(6) (IOB) : SLEW=FAST DRIVE=12
AD(7) (IOB) : SLEW=FAST DRIVE=12
AD(8) (IOB) : SLEW=FAST DRIVE=12
AD(9) (IOB) : SLEW=FAST DRIVE=12
Clk_SDp (IOB) : SLEW=FAST DRIVE=16
Reset (IOB)
data_addr_n (IOB)
sd_add(0) (IOB) : SLEW=FAST DRIVE=12
sd_add(1) (IOB) : SLEW=FAST DRIVE=12
sd_add(10) (IOB) : SLEW=FAST DRIVE=12
sd_add(2) (IOB) : SLEW=FAST DRIVE=12
sd_add(3) (IOB) : SLEW=FAST DRIVE=12
sd_add(4) (IOB) : SLEW=FAST DRIVE=12
sd_add(5) (IOB) : SLEW=FAST DRIVE=12
sd_add(6) (IOB) : SLEW=FAST DRIVE=12
sd_add(7) (IOB) : SLEW=FAST DRIVE=12
sd_add(8) (IOB) : SLEW=FAST DRIVE=12
sd_add(9) (IOB) : SLEW=FAST DRIVE=12
sd_ba (IOB) : SLEW=FAST DRIVE=12
sd_cas (IOB) : SLEW=FAST DRIVE=12
sd_cke (IOB) : SLEW=FAST DRIVE=12
sd_cs1 (IOB) : SLEW=FAST DRIVE=12
sd_cs2 (IOB) : SLEW=FAST DRIVE=12
sd_data(0) (IOB) : SLEW=FAST DRIVE=12
sd_data(1) (IOB) : SLEW=FAST DRIVE=12
sd_data(10) (IOB) : SLEW=FAST DRIVE=12
sd_data(11) (IOB) : SLEW=FAST DRIVE=12
sd_data(12) (IOB) : SLEW=FAST DRIVE=12
sd_data(13) (IOB) : SLEW=FAST DRIVE=12
sd_data(14) (IOB) : SLEW=FAST DRIVE=12
sd_data(15) (IOB) : SLEW=FAST DRIVE=12
sd_data(16) (IOB) : SLEW=FAST DRIVE=12
sd_data(17) (IOB) : SLEW=FAST DRIVE=12
sd_data(18) (IOB) : SLEW=FAST DRIVE=12
sd_data(19) (IOB) : SLEW=FAST DRIVE=12
sd_data(2) (IOB) : SLEW=FAST DRIVE=12
sd_data(20) (IOB) : SLEW=FAST DRIVE=12
sd_data(21) (IOB) : SLEW=FAST DRIVE=12
sd_data(22) (IOB) : SLEW=FAST DRIVE=12
sd_data(23) (IOB) : SLEW=FAST DRIVE=12
sd_data(24) (IOB) : SLEW=FAST DRIVE=12
sd_data(25) (IOB) : SLEW=FAST DRIVE=12
sd_data(26) (IOB) : SLEW=FAST DRIVE=12
sd_data(27) (IOB) : SLEW=FAST DRIVE=12
sd_data(28) (IOB) : SLEW=FAST DRIVE=12
sd_data(29) (IOB) : SLEW=FAST DRIVE=12
sd_data(3) (IOB) : SLEW=FAST DRIVE=12
sd_data(30) (IOB) : SLEW=FAST DRIVE=12
sd_data(31) (IOB) : SLEW=FAST DRIVE=12
sd_data(4) (IOB) : SLEW=FAST DRIVE=12
sd_data(5) (IOB) : SLEW=FAST DRIVE=12
sd_data(6) (IOB) : SLEW=FAST DRIVE=12
sd_data(7) (IOB) : SLEW=FAST DRIVE=12
sd_data(8) (IOB) : SLEW=FAST DRIVE=12
sd_data(9) (IOB) : SLEW=FAST DRIVE=12
sd_dqm(0) (IOB) : SLEW=FAST DRIVE=12
sd_dqm(1) (IOB) : SLEW=FAST DRIVE=12
sd_dqm(2) (IOB) : SLEW=FAST DRIVE=12
sd_dqm(3) (IOB) : SLEW=FAST DRIVE=12
sd_ras (IOB) : SLEW=FAST DRIVE=12
sd_we (IOB) : SLEW=FAST DRIVE=12
we_rn (IOB)

Section 11 - RPMs
-----------------

Section 12 - Guide Report
-------------------------
Guide not run on this design.

Section 13 - Area Group Summary
-------------------------------
No area groups were found in this design.