_primary.vhd

来自「The SDRAM controller is designed for the」· VHDL 代码 · 共 34 行

library verilog;
use verilog.vl_types.all;
entity mt48lc1m16a1 is
    generic(
        addr_bits       : integer := 11;
        data_bits       : integer := 16;
        col_bits        : integer := 8;
        mem_sizes       : integer := 524287;
        mode_bits       : integer := 11;
        tac             : real    := 7.500000;
        toh             : real    := 2.500000;
        thz             : integer := 8;
        tmrd            : integer := 2;
        trc             : integer := 80;
        tras            : integer := 50;
        trcd            : integer := 30;
        trp             : integer := 30;
        trrd            : integer := 20;
        twr             : integer := 1
    );
    port(
        dq              : inout  vl_logic_vector;
        addr            : in     vl_logic_vector;
        ba              : in     vl_logic;
        clk             : in     vl_logic;
        cke             : in     vl_logic;
        cs_n            : in     vl_logic;
        ras_n           : in     vl_logic;
        cas_n           : in     vl_logic;
        we_n            : in     vl_logic;
        dqm             : in     vl_logic_vector(1 downto 0)
    );
end mt48lc1m16a1;