📄 mx25l512.v
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//$display( $stime, " Enter Block Erase Function ...");
//dummy_cycle( 24 ); // to get 24 bits address
chip_erase;
//$display( $stime, " Leave Block Erase Function ...");
state <= `STANDBY_STATE;
end
else if ( si_reg[ 7:0 ] == CE1 || si_reg[ 7:0 ] == CE2 ) begin
//$display( $stime, " Enter Chip Erase Function ...");
chip_erase;
//$display( $stime, " Leave Chip Erase Function ...");
state <= `STANDBY_STATE;
end
else if ( si_reg[ 7:0 ] == PP ) begin
//$display( $stime, " Enter Page Program Function ...");
dummy_cycle( 24 ); // to get 24 bits address
setup_addr( si_reg, segment_addr, offset_addr );
page_program( segment_addr, offset_addr );
update_array( segment_addr, offset_addr );
//$display( $stime, " Leave Page Program Function ...");
state <= `STANDBY_STATE;
end
else if ( si_reg[ 7:0 ] == DP ) begin
//$display( $stime, " Enter Deep Power Dwon Function ...");
deep_power_down;
//$display( $stime, " Leave Deep Power Down Function ...");
state <= `STANDBY_STATE;
end
//else if ( si_reg[ 7:0 ] == EN4K ) begin
// //$display( $stime, " Enter Enter 4Kb Sector Function ...");
// enter_4kb_sector;
// //$display( $stime, " Leave Entor 4Kb Sector Function ...");
// state <= `STANDBY_STATE;
//end
//else if ( si_reg[ 7:0 ] == EX4K ) begin
// //$display( $stime, " Enter Exit 4Kb Sector Function ...");
// exit_4kb_sector;
// //$display( $stime, " Leave Exit 4Kb Sector Function ...");
// state <= `STANDBY_STATE;
//end
else if ( si_reg[ 7:0 ] == RDP || si_reg[ 7:0 ] == RES ) begin
//$display( $stime, " Enter Release from Deep Power Dwon Function ...");
release_from_deep_power_dwon;
//$display( $stime, " Leave Release from Deep Power Dwon Function ...");
state <= `STANDBY_STATE;
end
else if ( si_reg[ 7:0 ] == REMS ) begin
//$display( $stime, " Enter Read Electronic Manufacturer & ID Function ...");
dummy_cycle ( 16 ); // 2 dummy cycle
dummy_cycle ( 8 ); // 1 AD
read_electronic_manufacturer_device_id;
//$display( $stime, " Leave Read Electronic Manufacturer & ID Function ...");
state <= `STANDBY_STATE;
end
else begin
state <= #1 `BAD_CMD_STATE;
end
end
`BAD_CMD_STATE: begin
//SO <= #tSHQZ 1'bz;
SO_reg <= #tSHQZ 1'bz;
state <= #(tC-1) `BAD_CMD_STATE;
end
default: begin
SO_reg <= #tAA 1'bx;
state <= #(tC-1) `STANDBY_STATE;
end
endcase
end // else begin
end // always @( posedge SCLK or posedge CS ) begin
//////////////////////////////////////////////////////////////////////
// Module Task Declaration
//////////////////////////////////////////////////////////////////////
/*---------------------------------------------------------------*/
/* Description: define a wait dummy cycle task */
/* INPUT */
/* cnum: cycle number */
/*---------------------------------------------------------------*/
task dummy_cycle;
input [31:0] cnum;
begin
repeat( cnum ) begin
@( posedge SCLK );
end
end
endtask
/*---------------------------------------------------------------*/
/* Description: setup segment address and offset address from */
/* 4-byte serial input. */
/* INPUT */
/* si: 4-byte serial input */
/* OUTPUT */
/* segment: segment address */
/* offset : offset address */
/*---------------------------------------------------------------*/
task setup_addr;
input [23:0] si;
output [13:0] segment;
output [7:0] offset;
begin
#1;
{ offset[ 7:0 ] } = { si_reg[ 7:0 ] };
{ segment[ 13:0 ] } = { si_reg[ 23:8 ] };
end
endtask
/*---------------------------------------------------------------*/
/* Description: setup sector address */
/* INPUT */
/* si: 2-byte serial input */
/* OUTPUT */
/* sector: sector address */
/*---------------------------------------------------------------*/
task setup_sector;
input [23:0] si;
output [`SECTOR_ADDR -1:0] sector; // A[`SECTOR_ADDR -1:16] defines a sector
begin
#1;
{ sector[`SECTOR_ADDR -1:0 ] } = { si_reg[ 11:4 ] };
end
endtask
/*---------------------------------------------------------------*/
/* Description: define a write enable task */
/*---------------------------------------------------------------*/
task write_enable;
begin
//$display( $stime, " Old Status Register = %b", status_reg );
forever begin
@( posedge SCLK or posedge CS );
if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode
status_reg[1] = 1'b1;
//$display( $stime, " New Status Register = %b", status_reg );
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
end
disable write_enable;
end
else begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
end
end
end
end
endtask
/*---------------------------------------------------------------*/
/* Description: define a write disable task (WRDI) */
/*---------------------------------------------------------------*/
task write_disable;
begin
//$display( $stime, " Old Status Register = %b", status_reg );
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
end
forever begin
@( posedge SCLK or posedge CS );
if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
status_reg[1] = 1'b0;
//$display( $stime, " New Status Register = %b", status_reg );
end
disable write_disable;
end
else begin
end
end
end
endtask
/*---------------------------------------------------------------*/
/* Description: define a read id task (WRID) */
/*---------------------------------------------------------------*/
task read_id;
reg [ 23:0 ] dummy_ID;
integer dummy_count;
begin
dummy_ID = {ID_MXIC,8'h00,ID_Device};
dummy_count = 0;
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
forever begin
@( negedge SCLK or posedge CS );
if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end
else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
SO_reg <= #tCLQV 1'bz;
//SO = #tCLQV 1'bz;
end
disable read_id;
end
else begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if ( pmode == 1'b0) begin // check parallel mode (2)
{ SO_reg, dummy_ID } <= #tCLQV { dummy_ID, dummy_ID[ 23 ] };
end
else begin
if ( dummy_count == 0 ) begin
SO_reg <= #tCLQV ID_MXIC;
dummy_count = 1;
end
else if ( dummy_count == 1 ) begin
SO_reg <= #tCLQV 8'h00;
dummy_count = 2;
end
else if ( dummy_count == 2 ) begin
SO_reg <= #tCLQV ID_Device;
dummy_count = 0;
end
end
end
end
end // end forever
end
endtask
/*---------------------------------------------------------------*/
/* Description: define a read status task (WRSR) */
/*---------------------------------------------------------------*/
task read_status;
input [ 7:0 ] s_reg;
reg [ 7:0 ] dummy_reg;
integer dummy_count;
begin
dummy_reg = s_reg;
dummy_count = 8;
if ( dpmode == 1'b0) begin //do work on non deep power down mode
if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
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