mx25l8005.v

Verilog based simluation model for MXIC SPI Flash.

                            {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                        end
                        SO_reg <= #tCLQV 1'bz;
                        //SO = #tCLQV 1'bz;
                    end    
                    disable read_status;
                end
                else begin
                    if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                        if ( pmode == 1'b0 ) begin
                            if (dummy_count) begin
                                { SO_reg, dummy_reg } <= #tCLQV { dummy_reg, dummy_reg[ 7 ] };
                                dummy_count = dummy_count - 1;
                            end
                            else begin
                                      dummy_reg = s_reg;
                                      { SO_reg, dummy_reg } <= #tCLQV { dummy_reg, dummy_reg[ 7 ] };
                                      dummy_count = 7;
                            end          
                        end
                        else begin 
                                  SO_reg <= #tCLQV s_reg;
                        end
                    end    
                end
            end  // end forever
        end
    endtask

    /*---------------------------------------------------------------*/
    /*  Description: define a write status task                      */
    /*---------------------------------------------------------------*/
    task write_status;
         integer dummy_count;
        begin
            dummy_count=0;
            //$display( $stime, " Old Status Register = %b", status_reg );
            if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                if (pmode == 0) begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                end    
                else begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                end
            end    
            forever begin
               @( posedge SCLK or posedge CS );
               if ( CS == 1'b1 ) begin   
                   if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                       if (pmode == 0) begin
                           {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                       end    
                       else begin
                           {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                       end
                       if ( !(wp_reg ==1'b0 && status_reg[7]==1'b1) ) begin // do work on not PM (2)
                          if ( status_reg[1] == 1'b1 ) begin //WEL:Write Enable Latch (3)
                               if ( dummy_count == 8 ) begin
                                   if( (status_reg[7] == si_reg[7] ) && (status_reg[5:2] == si_reg[5:2] )) begin
                                      //WIP:Write Enable Latch
                                      status_reg[0]   <= 1'b1;
                                      status_reg[0]   <= #tW_WEL 1'b0;
                                      //WEL:Write Enable Latch
                                      status_reg[1]   <= #tW_WEL 1'b0;
                                   end   
                                   else begin
                                      //SRWD:Status Register Write Protect
                                      status_reg[7]   <= #tW_BP si_reg[7];
                                      status_reg[5:2] <= #tW_BP si_reg[5:2];
                                      //WIP:Write Enable Latch
                                      status_reg[0]   <= 1'b1;
                                      status_reg[0]   <= #tW_BP 1'b0;
                                      //WEL:Write Enable Latch
                                      status_reg[1]   <= #tW_BP 1'b0;
                                   end
                               end
                               else begin
                                   //WIP:Write Enable Latch
                                   status_reg[0]   <= 1'b1;
                                   status_reg[0]   <= #tW_WIP 1'b0;
                                   //WEL:Write Enable Latch
                                   status_reg[1]   <= #tW_WEL 1'b0;
                               end
                          end
                          else begin // do not work on WEL = 1'b0
                               //WEL:Write Enable Latch
                               status_reg[1]   <= #tW_WEL 1'b0;
                          end
                       end     
                       else begin
                            //WEL:Write Enable Latch
                            status_reg[1]   = 1'b0;
                       //$display( $stime, " New Status Register = %b", status_reg );
                       end 
		   end  
                   disable write_status;
               end
               else begin
                   if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                       dummy_count = dummy_count + 1;
                   end    
               end
            end // end forever    
        end
    endtask
    
    /*---------------------------------------------------------------*/
    /*  Description: define a read data task                         */
    /*---------------------------------------------------------------*/
    task read_data;

        reg  [`FLASH_ADDR - 1:0]      rom_addr;    // rom_addr = {segment, offset}
        integer dummy_count, tmp_int;
        reg  [7:0]       out_buf;
        begin
            dummy_count = 8;
            rom_addr = si_reg[23:0];
            if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                if (pmode == 0) begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b0,1'b1,1'b0};
                end    
                else begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b0,1'b0,1'b1};
                end
                    out_buf = ROM_ARRAY[ rom_addr ]; 
            end 
            forever begin
                @( negedge SCLK or posedge CS );
                if ( CS == 1'b1 ) begin
                    if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                        if (pmode == 0) begin
                            {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                        end    
                        else begin
                            {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                        end
                        SO_reg <= #tCLQV 1'bz;
                    end
                    disable read_data;
                end 
                else if ( status_reg[0] == 1'b0 ) begin //WIP:write in rpocess bit = 0 (1)
                         if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                                 if ( dummy_count ) begin
                                          { SO_reg, out_buf } <= #tCLQV { out_buf, out_buf[6] };
                                          dummy_count = dummy_count - 1;
                                 end
                                 else begin
                                           rom_addr = rom_addr + 1;
                                               out_buf = ROM_ARRAY[ rom_addr ]; 
                                           { SO_reg, out_buf } <= #tCLQV { out_buf, out_buf[6] };
                                           dummy_count = 7 ;
                                 end 
                         end    
                end    
            end  // end forever
        end   
    endtask

    /*---------------------------------------------------------------*/
    /*  Description: define a fast read data task                    */
    /*               0B AD1 AD2 AD3 X                                */
    /*---------------------------------------------------------------*/
    task fast_read_data;

        reg  [`FLASH_ADDR - 1:0]      rom_addr;    // rom_addr = {segment, offset}
        integer dummy_count, tmp_int;
        reg  [7:0]       out_buf;
        begin
            dummy_count = 8;
            rom_addr = si_reg[23:0];
            if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                out_buf = ROM_ARRAY[ rom_addr ]; 
                if (pmode == 0) begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                end    
                else begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                end
            end
            dummy_cycle( 8 );  
            forever begin
                @( negedge SCLK or posedge CS );
                if ( CS == 1'b1 ) begin
                    if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                        SO_reg <= #tCLQV 1'bz; 
                        if (pmode == 0) begin
                            {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                        end    
                        else begin
                            {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                        end
                    end   
                    disable fast_read_data;
                end 
                else if ( status_reg[0] == 1'b0 ) begin //WIP:write in rpocess bit = 0 (1)
                         if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                                 if ( dummy_count ) begin
                                          { SO_reg, out_buf } <= #tCLQV { out_buf, out_buf[6] };
                                          dummy_count = dummy_count - 1;
                                 end
                                 else begin
                                           rom_addr = rom_addr + 1;
                                           out_buf = ROM_ARRAY[ rom_addr ]; 
                                           { SO_reg, out_buf } <= #tCLQV { out_buf, out_buf[6] };
                                           dummy_count = 7 ;
                                 end 
                         end    
                end    
            end  // end forever
        end   
    endtask
    
    /*---------------------------------------------------------------*/
    /*  Description: define a parallel mode task                     */
    /*---------------------------------------------------------------*/
//    task parallel_mode;
//        begin
//            @( posedge CS );
//            if( CS == 1'b1 ) begin
//               if ( dpmode == 1'b0) begin //do work on non deep power down mode 
//                   //$display( $stime, " Old Pmode Register = %b", pmode );
//                   pmode = 1;
//                   {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
//                   //$display( $stime, " New Pmode Register = %b", pmode );
//               end    
//            end  
//        end
//    endtask
//
    /*---------------------------------------------------------------*/
    /*  Description: define a block erase task                       */
    /*               D8 AD1 AD2 AD3                                  */
    /*---------------------------------------------------------------*/
    task block_erase;
        reg [`BLOCK_ADDR - 1:0] block; 
        reg [15:0] offset; // 64K Byte
        reg [`FLASH_ADDR - 1:0] rom_addr;
        
        integer i, start_addr,end_addr,start_4kb_addr,end_4kb_addr;
        reg bp0;
        reg bp1;
        reg bp2;
        reg bp3;
        begin
            block[`BLOCK_ADDR - 1:0] = si_reg[19:16];
            offset = 16'h0;
            start_addr = (si_reg[19:16]<<16) + 16'h0;
            end_addr = (si_reg[19:16]<<16) + 16'hf;            
            if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                if (pmode == 0) begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                end    
                else begin
                    {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                end
            end    
            forever begin
             @( posedge CS );
               if( CS == 1'b1 ) begin
                  if ( dpmode == 1'b0) begin //do work on non deep power down mode 
                      if (pmode == 0) begin
                          {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
                      end    
                      else begin
                          {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
                      end
                      if(wp_reg==1'b0||status_reg[7]==1'b1) begin
                         // Protected Mode
                      end 
                      else if(dpmode == 1'b1) begin
                         // deep power down mode
                      end
                      else begin   
                           if ( protected_area({block[`BLOCK_ADDR - 1:0],4'b0}) == 1'b1) begin
                           end 
                           else if ( 16 <= block && block <=31 && bp2==1'b1 && bp1==1'b0 && bp0 ==1'b1) begin
                           end
                           else begin
                                //WIP : write in process bit