iir.vhd

VHDL的IIR数字滤波器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity iir is
port(clk,reset:in std_logic;
x:in signed(15 downto 0);
y:out signed(15 downto 0));
end iir;
architecture behave of iir is
component iirs0
port(clk,reset:in std_logic;
x:in signed(15 downto 0);
y:out signed(15 downto 0));
end component;
component iirs1
port(clk,reset:in std_logic;
x:in signed(15 downto 0);
y:out signed(15 downto 0));
end component;
signal y0:signed(15 downto 0);
begin
u0:iirs0 port map(clk,reset,x,y0);
u1:iirs1 port map(clk,reset,y0,y);
end behave;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
package coeffs0 is
type coef_arr is array(0 to 2) of signed(15 downto 0);
constant coefs11: coef_arr:=(b"0010000000000000",b"0100000000000000",b"0010000000000000");
type coef_arr1 is array(0 to 1) of signed(15 downto 0);
constant coefs12: coef_arr1:= (b"0011111100010001", b"0001111100010101");
constant coefs22: coef_arr1:= (b"0011111111100011", b"0001111111100101");
end coeffs0;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.coeffs0.all;
entity iirs0 is
port(clk,reset:in std_logic;
x:in signed(15 downto 0);
y:out signed(15 downto 0));
end iirs0;
architecture beh of iirs0 is
begin
main:process(clk,reset)
type shift_arr is array(2 downto 0) of signed(15 downto 0);
type shift_arr1 is array (2 downto 0) of signed(15 downto 0);
variable tmp:signed(15 downto 0);
variable acc:signed(31 downto 0);
variable shift:shift_arr;
variable shift1:shift_arr1;
begin
if reset='1'then
for i in 0 to 2 loop
shift(i):=(others=>'0');
end loop;
for i in 0 to 1 loop
shift1(i):=(others=>'0');
end loop;
y<=(others=>'0');
elsif clk'event and clk='1' then
tmp:=x;
acc:=tmp*coefs11(0)-shift(1)*coefs11(1)+shift(0)*coefs11(2)+shift1(1)*coefs12(0)-shift1(0)*coefs12(1);
y<=acc(28 downto 13);
shift1(2):=acc(28 downto 13);
shift(2):=tmp;
for i in 0 to 1 loop
shift(i):=shift(i+1);
shift1(i):=shift1(i+1);
end loop;
end if;
end process;
end beh;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.coeffs0.all;
entity iirs1 is
port(clk,reset:in std_logic;
x:in signed(15 downto 0);
y:out signed(15 downto 0));
end iirs1;
architecture beh of iirs1 is
begin
main:process(clk,reset)
type shift_arr is array(2 downto 0) of signed(15 downto 0);
type shift_arr1 is array (2 downto 0) of signed(15 downto 0);
variable tmp:signed(15 downto 0);
variable acc:signed(31 downto 0);
constant a:signed(15 downto 0):=b"0001110000010011";
variable c:signed(31 downto 0);
variable b:signed(15 downto 0);
variable shift:shift_arr;
variable shift1:shift_arr1;
begin
if reset='1'then
for i in 0 to 2 loop
shift(i):=(others=>'0');
end loop;
for i in 0 to 1 loop
shift1(i):=(others=>'0');
end loop;
y<=(others=>'0');
elsif clk'event and clk='1' then
tmp:=x;
acc:=tmp*coefs11(0)-shift(1)*coefs11(1)+shift(0)*coefs11(2)+shift1(1)*coefs22(0)-shift1(0)*coefs22(1);
b:=acc(28 downto 13);
shift1(2):=acc(28 downto 13);
shift(2):=tmp;
c:=b*a;
y<=c(28 downto 13);
for i in 0 to 1 loop
shift(i):=shift(i+1);
shift1(i):=shift1(i+1);
end loop;
end if;
end process;
end beh;