testbench.vhd

VHDL的IIR数字滤波器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity testbench is
    constant ClockPeriod: time := 40 ns;
end testbench;

architecture testbenchArc of testbench is
    component iir is
        port(clk: in std_logic;
            reset: in std_logic;
            x:in signed(15 downto 0);
            y:out signed(15 downto 0));
    end component iir;
    
    signal clk,reset: std_logic;
    signal x,y: signed(15 downto 0);
begin
    CounterInstance: iir port map(clk,reset,x,y);
    
    simProcess: process
    begin
        reset <= '1';
        wait for 50 ns;
        reset <= '0';
       wait for 10000 ns;
        reset <= '1';
    end process simprocess;
   
   process
    begin 
    --x <= b"0010000000000000" ;
     --wait for 80 ns;
    x <= b"0001001100110011" ;
    wait for 80 ns;
    x <= b"0001011001010111" ;
     wait for 80 ns;
    x <= b"0001100101111001" ;
     wait for 80 ns;
    x <= b"0001110010010111" ;
     wait for 80 ns;
    x <= b"0001111110110000" ;
     wait for 80 ns;
    x <= b"0010001011000000" ;
     wait for 80 ns;
    x <= b"0010010111000111" ;
     wait for 80 ns;
    x <= b"0010100011000011" ;
     wait for 80 ns;
    x <= b"0010101110110001" ;
     wait for 80 ns;
    x <= b"0010111010010000" ;
     wait for 80 ns;
    x <= b"0011000101011111" ;
     wait for 80 ns;
    x <= b"0011010000011010" ;
     wait for 80 ns;
    x <= b"0011011011000010" ;
     wait for 80 ns;
  end process;
    
    ClockProcess: process(clk, reset)
    begin
        if (reset = '1') then
            clk <= '0';
        else
            clk <= not clk after ClockPeriod;
        end if;
    end process ClockProcess;
    
end testbenchArc;