main.tan.qmsg

采用Verilog HDL语言编写的直流电动机控制系统

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk_SCL " "Info: Assuming node \"Clk_SCL\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clk_SCL" } } } }  } 0}  } {  } 0}