data_read.tan.qmsg

采用Verilog HDL语言编写的直流电动机控制系统

{ "Info" "ITDB_FULL_TCO_RESULT" "Adc_SCL Current_Data\[4\] Data\[8\] 6.900 ns register " "Info: tco from clock \"Adc_SCL\" to destination pin \"Current_Data\[4\]\" through register \"Data\[8\]\" is 6.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Adc_SCL source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"Adc_SCL\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_SCL 1 CLK PIN_39 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 19; CLK Node = 'Adc_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_SCL } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Data\[8\] 2 REG LC6_B2 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC6_B2; Fanout = 1; REG Node = 'Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.200 ns" { Adc_SCL Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[8] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Longest register pin " "Info: + Longest register to pin delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Data\[8\] 1 REG LC6_B2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B2; Fanout = 1; REG Node = 'Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.800 ns) 5.100 ns Current_Data\[4\] 2 PIN PIN_16 0 " "Info: 2: + IC(1.300 ns) + CELL(3.800 ns) = 5.100 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'Current_Data\[4\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "5.100 ns" { Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 74.51 % " "Info: Total cell delay = 3.800 ns ( 74.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns 25.49 % " "Info: Total interconnect delay = 1.300 ns ( 25.49 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "5.100 ns" { Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Data[8] Current_Data[4] } { 0.000ns 1.300ns } { 0.000ns 3.800ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[8] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "5.100 ns" { Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Data[8] Current_Data[4] } { 0.000ns 1.300ns } { 0.000ns 3.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Data\[15\] Adc_Sdata Adc_SCL 0.500 ns register " "Info: th for register \"Data\[15\]\" (data pin = \"Adc_Sdata\", clock pin = \"Adc_SCL\") is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Adc_SCL destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"Adc_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_SCL 1 CLK PIN_39 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 19; CLK Node = 'Adc_SCL'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_SCL } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Data\[15\] 2 REG LC4_B2 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'Data\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.200 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[15] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_Sdata 1 PIN PIN_91 12 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 12; PIN Node = 'Adc_Sdata'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_Sdata } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 1.700 ns Data\[15\] 2 REG LC4_B2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'Data\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.400 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 100.00 % " "Info: Total cell delay = 1.700 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.700 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { Adc_Sdata Adc_Sdata~out Data[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[15] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.700 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { Adc_Sdata Adc_Sdata~out Data[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 03 20:40:08 2006 " "Info: Processing ended: Thu Aug 03 20:40:08 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}