trafficlight.fit.summary

采用Verilog HDL语言编写的交通灯控制系统

Flow Status : Successful - Sun May 28 11:10:16 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : trafficlight
Top-level Entity Name : trafficlight
Family : Cyclone
Met timing requirements : N/A
Total logic elements : 152 / 2,910 ( 5 % )
Total pins : 19 / 65 ( 29 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )
Device : EP1C3T100C6
Timing Models : Final