trafficlight.fit.qmsg

采用Verilog HDL语言编写的交通灯控制系统

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "18 unused 3.30 2 16 0 " "Info: Number of I/O pins in group: 18 (unused VREF, 3.30 VCCIO, 2 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.459 ns register register " "Info: Estimated most critical path is register to register delay of 2.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan:inst\|sdata\[0\] 1 REG LAB_X19_Y6 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y6; Fanout = 19; REG Node = 'scan:inst\|sdata\[0\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { scan:inst|sdata[0] } "NODE_NAME" } "" } } { "scan.v" "" { Text "F:/dolphin/trafficlight/scan.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.340 ns) 1.091 ns counter55:inst2\|CData0\[0\]~21 2 COMB LAB_X19_Y8 8 " "Info: 2: + IC(0.751 ns) + CELL(0.340 ns) = 1.091 ns; Loc. = LAB_X19_Y8; Fanout = 8; COMB Node = 'counter55:inst2\|CData0\[0\]~21'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.091 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 } "NODE_NAME" } "" } } { "counter55.v" "" { Text "F:/dolphin/trafficlight/counter55.v" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.512 ns) + CELL(0.856 ns) 2.459 ns counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[0\] 3 REG LAB_X20_Y8 6 " "Info: 3: + IC(0.512 ns) + CELL(0.856 ns) = 2.459 ns; Loc. = LAB_X20_Y8; Fanout = 6; REG Node = 'counter55:inst2\|lpm_counter:CData0_rtl_0\|cntr_0b7:auto_generated\|safe_q\[0\]'" {  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "1.368 ns" { counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_0b7.tdf" "" { Text "F:/dolphin/trafficlight/db/cntr_0b7.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.196 ns 48.64 % " "Info: Total cell delay = 1.196 ns ( 48.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.263 ns 51.36 % " "Info: Total interconnect delay = 1.263 ns ( 51.36 % )" {  } {  } 0}  } { { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "2.459 ns" { scan:inst|sdata[0] counter55:inst2|CData0[0]~21 counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated|safe_q[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEG_Data\[0\] GND " "Info: Pin SEG_Data\[0\] has GND driving its datain port" {  } { { "trafficlight.bdf" "" { Schematic "F:/dolphin/trafficlight/trafficlight.bdf" { { 760 784 960 776 "SEG_Data\[7..0\]" "" } } } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SEG_Data\[0\]" } } } } { "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" "" { Report "F:/dolphin/trafficlight/db/trafficlight_cmp.qrpt" Compiler "trafficlight" "UNKNOWN" "V1" "F:/dolphin/trafficlight/db/trafficlight.quartus_db" { Floorplan "F:/dolphin/trafficlight/" "" "" { SEG_Data[0] } "NODE_NAME" } "" } } { "F:/dolphin/trafficlight/trafficlight.fld" "" { Floorplan "F:/dolphin/trafficlight/trafficlight.fld" "" "" { SEG_Data[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 28 11:10:16 2006 " "Info: Processing ended: Sun May 28 11:10:16 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}