perictr.vhd

cpld

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Mon May 09 09:11:57 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;


--  Entity Declaration

ENTITY perictr IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		PB_RS : IN STD_LOGIC;
		
		A0    :IN STD_LOGIC;
		A15 : IN STD_LOGIC;
		A16 : IN STD_LOGIC;
		A17 : IN STD_LOGIC;
		A18 : IN STD_LOGIC;
		A19 : IN STD_LOGIC;
		A20 : IN STD_LOGIC;
		
		DSP_RW : IN STD_LOGIC;
		FLASH_RY : IN STD_LOGIC;
		
		FPS_WAIT : IN STD_LOGIC;
		FPS_INTR : IN STD_LOGIC;
		XF : IN STD_LOGIC;
		DSP_DS : IN STD_LOGIC;
		DSP_PS : IN STD_LOGIC;
		DSP_IS : IN STD_LOGIC;
		DSP_MSTRB : IN STD_LOGIC;
		IOSTRB : IN STD_LOGIC;
		BDX2 : IN STD_LOGIC;
		CPLD_TOUT : IN STD_LOGIC;
		CPLD_CLKIN : IN STD_LOGIC;
		CPLD_GCLRN : IN STD_LOGIC;
		CPLD_OE1 : IN STD_LOGIC;
		
		RS : OUT STD_LOGIC;
		INT1 : OUT STD_LOGIC;
	--	INT2 : OUT STD_LOGIC;
		INT3 : OUT STD_LOGIC;
		NMI : OUT STD_LOGIC;
		HOLD : OUT STD_LOGIC;
		FLASH_A15 : OUT STD_LOGIC;
		FLASH_A16 : OUT STD_LOGIC;
		FLASH_A17 : OUT STD_LOGIC;
		FLASH_BYTE : OUT STD_LOGIC;
		CSROM : OUT STD_LOGIC;
		FLASH_WR : OUT STD_LOGIC;
		FLASH_RD : OUT STD_LOGIC;
		FLASH_RS : OUT STD_LOGIC;
		FPS_A0 : OUT STD_LOGIC;
		CS_FPS : OUT STD_LOGIC;
		FPS_RD : OUT STD_LOGIC;
		FPS_WR : OUT STD_LOGIC;
		FPS_EXINT : OUT STD_LOGIC;
		CSRAM : OUT STD_LOGIC;
		BIO : OUT STD_LOGIC;
		DSP_READY : OUT STD_LOGIC;
		BDR2 :   OUT STD_LOGIC;
		BCLKR2 : OUT STD_LOGIC;
		BCLKX2 : IN STD_LOGIC;
		BFSR2 : OUT STD_LOGIC;
		BFSX2 : IN STD_LOGIC;
		HD0,HD1,HD2,HD3,HD4,HD5,HD6,HD7:OUT STD_LOGIC 
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END perictr;


--  Architecture Body

ARCHITECTURE perictr_architecture OF perictr IS

	
BEGIN

--************
--RAM connect:
--Note:
--A19=A180:select external RAM;
--A19=0,A18=1:select FLASH;
--************

   
   CSRAM<= A20 OR A19 OR A18 OR DSP_MSTRB;--DSP_MSTRB=low  address external memeory
                            --0 0000

--*******************
                   
--interrupt and reset
--*******************

INT1<='1';--'1' AND FPS_INTR;
--INT2<='Z';-----键盘中断
INT3<='1';
HOLD<='1';
NMI<='1'; 
RS<='1' ;

--**************

--flash connect:
--**************
FLASH_A15<=A15;
FLASH_A16<=A16;
FLASH_A17<=A17;                                                                                                                                                
FLASH_BYTE<='1';--select 16 bit mode  (0=BYTE;1=WORD)                                                                                                         
CSROM<=A20 OR A19 OR (NOT A18) OR DSP_MSTRB;  --0 0100
FLASH_WR<=DSP_RW;
FLASH_RD<=NOT DSP_RW;
FLASH_RS<=PB_RS;

--************  
 
--FPS connect:
--************

FPS_A0<=A0;
CS_FPS<=DSP_IS;               --CS0,chip select low active
FPS_RD<= NOT DSP_RW;
FPS_WR<=DSP_RW;
DSP_READY<=FPS_WAIT OR FLASH_RY;--high  active!
FPS_EXINT<='Z';
--******************
--     HPI接口
--******************

HD0<='Z';
HD1<='Z';
HD2<='Z';
HD3<='Z';
HD4<='Z';
HD5<='Z';
HD6<='Z';
HD7<='Z';

BIO <='Z';
BDR2 <='Z';
BCLKR2 <='Z';
--BCLKX2 <='Z';
BFSR2 <='Z';
--BFSX2 <='Z';

END perictr_architecture;