readkeyvalblock.vhd

cpld

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-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Mon May 09 18:22:55 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.TYPES.ALL;


--  Entity Declaration

ENTITY ReadKeyValBlock IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		--CPLD_CLKIN : IN STD_LOGIC;
		Key_CLK    :IN STD_LOGIC;
		Key : IN STD_LOGIC;
		iKey_SDAT : IN STD_LOGIC;
		Read_En : IN STD_LOGIC;
		
		Key_Data :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		Wr_Addr: OUT  STD_LOGIC;
		Wr:OUT STD_LOGIC;
		DSP_Write_INT : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END ReadKeyValBlock;


--  Architecture Body

ARCHITECTURE ReadKeyValBlock_architecture OF ReadKeyValBlock IS

--SIGNAL Define

SIGNAL Recieve_Cnt:INTEGER RANGE 0 TO 255;
SIGNAL INPUT_Register:STD_LOGIC_VECTOR(7 DOWNTO 0); 
SIGNAL Recieve_Over: STD_LOGIC;
SIGNAL DSP_Read_Over:STD_LOGIC;
SIGNAL INT2:STD_LOGIC; 
SIGNAL SRAM_SEL:STD_LOGIC;
SIGNAL Read_Done:STD_LOGIC;
-------------------------------------------------
--存储器定义：
SUBTYPE BYTE    IS STD_LOGIC_VECTOR(7 DOWNTO 0) ;
TYPE    MEMORY  IS ARRAY (0 TO 2)  OF BYTE;
SIGNAL SRAM:   MEMORY;
SIGNAL ADR_IN:  INTEGER RANGE 0 TO 7;
-------------------------------------------------

BEGIN 

--------------------------------------
--=============================
--接收计数器
--=============================
Rx_CNT:PROCESS(Key_CLK) 

 BEGIN
 
      IF rising_edge(Key_CLK) THEN

            IF Key='0' AND Read_En='1'   THEN
         
                  Recieve_Cnt<=Recieve_Cnt+1;
          
            END IF;

           IF Key='1' THEN 
    
                  Recieve_Cnt<=0;   
  
   		   END IF;   

     END IF;
    
END PROCESS Rx_CNT;
--==============================================================================
--从7279A接收串口键值
--==============================================================================
Recieve_Key_Value: PROCESS(Key_CLK)
BEGIN

     IF falling_edge(Key_CLK) THEN

  	      IF Read_En='1' AND Recieve_Cnt<=8 THEN  
            
              	 INPUT_Register(0)<=iKey_SDAT;    
				 INPUT_Register(7 DOWNTO 1)<=INPUT_Register(6 DOWNTO 0); 

          END IF; 

          IF Recieve_Cnt=8  THEN   
                                                                                                                                                                                                                                                                                                                                                                                        
                 Read_Done<='1';  
            
          ELSE

                 Read_Done<='0'; 
         
          END IF;
    
     END IF;

END PROCESS Recieve_Key_Value;

--=============================================================

Write_KeyValue_SRAM:

 PROCESS(Key_CLK,Read_Done) 

BEGIN 
     IF rising_edge(Key_CLK) THEN 

        IF Read_Done='1' THEN
         
              Wr<='1'; 
              Wr_Addr<='0';--数据存在ram(0)
              Key_Data<=INPUT_Register;
             -- Key_Data<="10101010";

         END IF;

   END IF; 

END PROCESS Write_KeyValue_SRAM;

---------------------------------------------------
Create_INT2:
PROCESS(Key_CLK,Recieve_Cnt)--Read_Done,Recieve_Over

 BEGIN
     
      IF falling_edge(Key_CLK)  THEN

          IF Recieve_Cnt=10 THEN
           
              DSP_Write_INT<='0';

           ELSE 

              DSP_Write_INT<='1';
                 
          END IF;

      END IF;

END PROCESS Create_INT2;  

---------------------------------------------------       

----------------------------------------------------      
END ReadKeyValBlock_architecture;