inter.hier_info

cpld

|Inter|LCD_Display:inst5
CPLD_CLKIN => falling_edge~0.IN0
DSP_MSTRB => Create_LCD_En~0.IN0
DSP_RW => LCD_RW~0.DATAIN
DSP_RW => Create_LCD_En~2.IN0
A18 => Addr_Code[0].DATAIN
A19 => Addr_Code[1].DATAIN
A20 => LCD_RW~0.OE
A20 => Addr_Code[1].OE
A20 => Addr_Code[0].OE
A20 => Create_LCD_En~1.IN0
LCD_RS <= LCD_RS~0.DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_CS1 <= LCD_CS1~0.DB_MAX_OUTPUT_PORT_TYPE
LCD_CS2 <= LCD_CS2~0.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst
data[0] => altdpram:altdpram_component.data[0]
data[1] => altdpram:altdpram_component.data[1]
data[2] => altdpram:altdpram_component.data[2]
data[3] => altdpram:altdpram_component.data[3]
data[4] => altdpram:altdpram_component.data[4]
data[5] => altdpram:altdpram_component.data[5]
data[6] => altdpram:altdpram_component.data[6]
data[7] => altdpram:altdpram_component.data[7]
wraddress[0] => altdpram:altdpram_component.wraddress[0]
rdaddress[0] => altdpram:altdpram_component.rdaddress[0]
wren => altdpram:altdpram_component.wren
rden => altdpram:altdpram_component.rden
q[0] <= altdpram:altdpram_component.q[0]
q[1] <= altdpram:altdpram_component.q[1]
q[2] <= altdpram:altdpram_component.q[2]
q[3] <= altdpram:altdpram_component.q[3]
q[4] <= altdpram:altdpram_component.q[4]
q[5] <= altdpram:altdpram_component.q[5]
q[6] <= altdpram:altdpram_component.q[6]
q[7] <= altdpram:altdpram_component.q[7]


|Inter|altdpram0:inst|altdpram:altdpram_component
wren => lpm_decode:wdecoder.enable
data[0] => cells[1][0].DATAIN
data[0] => cells[0][0].DATAIN
data[1] => cells[1][1].DATAIN
data[1] => cells[0][1].DATAIN
data[2] => cells[1][2].DATAIN
data[2] => cells[0][2].DATAIN
data[3] => cells[1][3].DATAIN
data[3] => cells[0][3].DATAIN
data[4] => cells[1][4].DATAIN
data[4] => cells[0][4].DATAIN
data[5] => cells[1][5].DATAIN
data[5] => cells[0][5].DATAIN
data[6] => cells[1][6].DATAIN
data[6] => cells[0][6].DATAIN
data[7] => cells[1][7].DATAIN
data[7] => cells[0][7].DATAIN
wraddress[0] => lpm_decode:wdecoder.data[0]
inclock => ~NO_FANOUT~
inclocken => ~NO_FANOUT~
rden => xql[7].LATCH_ENABLE
rden => xql[6].LATCH_ENABLE
rden => xql[5].LATCH_ENABLE
rden => xql[4].LATCH_ENABLE
rden => xql[3].LATCH_ENABLE
rden => xql[2].LATCH_ENABLE
rden => xql[1].LATCH_ENABLE
rden => xql[0].LATCH_ENABLE
rdaddress[0] => lpm_mux:mux.sel[0]
outclock => ~NO_FANOUT~
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
q[0] <= xql[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= xql[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= xql[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= xql[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= xql[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= xql[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= xql[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= xql[7].DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux
data[0][0] => muxlut:$00009.data[0]
data[0][1] => muxlut:$00011.data[0]
data[0][2] => muxlut:$00013.data[0]
data[0][3] => muxlut:$00015.data[0]
data[0][4] => muxlut:$00017.data[0]
data[0][5] => muxlut:$00019.data[0]
data[0][6] => muxlut:$00021.data[0]
data[0][7] => muxlut:$00023.data[0]
data[1][0] => muxlut:$00009.data[1]
data[1][1] => muxlut:$00011.data[1]
data[1][2] => muxlut:$00013.data[1]
data[1][3] => muxlut:$00015.data[1]
data[1][4] => muxlut:$00017.data[1]
data[1][5] => muxlut:$00019.data[1]
data[1][6] => muxlut:$00021.data[1]
data[1][7] => muxlut:$00023.data[1]
sel[0] => muxlut:$00023.select[0]
sel[0] => muxlut:$00021.select[0]
sel[0] => muxlut:$00019.select[0]
sel[0] => muxlut:$00017.select[0]
sel[0] => muxlut:$00015.select[0]
sel[0] => muxlut:$00013.select[0]
sel[0] => muxlut:$00011.select[0]
sel[0] => muxlut:$00009.select[0]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= altshift:external_latency_ffs.result[0]
result[1] <= altshift:external_latency_ffs.result[1]
result[2] <= altshift:external_latency_ffs.result[2]
result[3] <= altshift:external_latency_ffs.result[3]
result[4] <= altshift:external_latency_ffs.result[4]
result[5] <= altshift:external_latency_ffs.result[5]
result[6] <= altshift:external_latency_ffs.result[6]
result[7] <= altshift:external_latency_ffs.result[7]


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|altshift:external_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00009
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00011
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00013
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00015
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00017
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00019
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00021
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_mux:mux|muxlut:$00023
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_decode:wdecoder
data[0] => decode_ngb:auto_generated.data[0]
enable => decode_ngb:auto_generated.enable
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
eq[0] <= decode_ngb:auto_generated.eq[0]
eq[1] <= decode_ngb:auto_generated.eq[1]


|Inter|altdpram0:inst|altdpram:altdpram_component|lpm_decode:wdecoder|decode_ngb:auto_generated
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE