inter.hier_info

cpld

|Inter
RS <= perictr:inst1.RS
PB_RS => perictr:inst1.PB_RS
PB_RS => CLK_DIV:inst6.PB_RS
A16 => perictr:inst1.A16
A17 => perictr:inst1.A17
DSP_RW => perictr:inst1.DSP_RW
DSP_RW => inst7.IN0
FLASH_RY => perictr:inst1.FLASH_RY
FPS_WAIT => perictr:inst1.FPS_WAIT
FPS_INTR => perictr:inst1.FPS_INTR
XF => perictr:inst1.XF
DSP_DS => perictr:inst1.DSP_DS
DSP_PS => perictr:inst1.DSP_PS
DSP_IS => perictr:inst1.DSP_IS
DSP_MSTRB => perictr:inst1.DSP_MSTRB
DSP_MSTRB => LCD_Display:inst5.DSP_MSTRB
IOSTRB => perictr:inst1.IOSTRB
BDX2 => perictr:inst1.BDX2
CPLD_GCLRN => perictr:inst1.CPLD_GCLRN
CPLD_OE1 => perictr:inst1.CPLD_OE1
BCLKX2 => perictr:inst1.BCLKX2
BFSX2 => perictr:inst1.BFSX2
CPLD_TOUT => perictr:inst1.CPLD_TOUT
CPLD_CLKIN => perictr:inst1.CPLD_CLKIN
CPLD_CLKIN => CLK_DIV:inst6.CPLD_CLKIN
CPLD_CLKIN => LCD_Display:inst5.CPLD_CLKIN
A18 => perictr:inst1.A18
A18 => LCD_Display:inst5.A18
A20 => perictr:inst1.A20
A20 => inst8.IN0
A19 => perictr:inst1.A19
A19 => inst7.IN2
A15 => perictr:inst1.A15
A15 => inst7.IN3
A0 => perictr:inst1.A0
A0 => altdpram0:inst.rdaddress[0]
INT1 <= perictr:inst1.INT1
INT3 <= perictr:inst1.INT3
NMI <= perictr:inst1.NMI
HOLD <= perictr:inst1.HOLD
FLASH_A15 <= perictr:inst1.FLASH_A15
FLASH_A16 <= perictr:inst1.FLASH_A16
FLASH_A17 <= perictr:inst1.FLASH_A17
FLASH_BYTE <= perictr:inst1.FLASH_BYTE
CSROM <= perictr:inst1.CSROM
FLASH_WR <= perictr:inst1.FLASH_WR
FLASH_RD <= perictr:inst1.FLASH_RD
FLASH_RS <= perictr:inst1.FLASH_RS
FPS_A0 <= perictr:inst1.FPS_A0
CS_FPS <= perictr:inst1.CS_FPS
FPS_RD <= perictr:inst1.FPS_RD
FPS_WR <= perictr:inst1.FPS_WR
FPS_EXINT <= perictr:inst1.FPS_EXINT
CSRAM <= perictr:inst1.CSRAM
BIO <= perictr:inst1.BIO
DSP_READY <= perictr:inst1.DSP_READY
BDR2 <= perictr:inst1.BDR2
DSP_Write_INT2 <= int2.DB_MAX_OUTPUT_PORT_TYPE
Key => ReadKeyValBlock:inst4.Key
Key => Send_CMD_7279A:inst3.Key
Key_RESET => Send_CMD_7279A:inst3.Key_RESET
Key_SDAT <= Send_CMD_7279A:inst3.oKey_SDAT
Key_CS <= cs.DB_MAX_OUTPUT_PORT_TYPE
LCD_RS <= LCD_Display:inst5.LCD_RS
LCD_RW <= LCD_Display:inst5.LCD_RW
LCD_E <= LCD_Display:inst5.LCD_E
LCD_CS1 <= LCD_Display:inst5.LCD_CS1
LCD_CS2 <= LCD_Display:inst5.LCD_CS2
BCLKR2 <= perictr:inst1.BCLKR2
BFSR2 <= perictr:inst1.BFSR2
HD0 <= perictr:inst1.HD0
HD1 <= perictr:inst1.HD1
HD2 <= perictr:inst1.HD2
HD3 <= perictr:inst1.HD3
HD4 <= perictr:inst1.HD4
HD5 <= perictr:inst1.HD5
HD6 <= perictr:inst1.HD6
HD7 <= tclk.DB_MAX_OUTPUT_PORT_TYPE
Key_CLKOUT <= clkout.DB_MAX_OUTPUT_PORT_TYPE
DATA_IO[0] <= altdpram0:inst.q[0]
DATA_IO[1] <= altdpram0:inst.q[1]
DATA_IO[2] <= altdpram0:inst.q[2]
DATA_IO[3] <= altdpram0:inst.q[3]
DATA_IO[4] <= altdpram0:inst.q[4]
DATA_IO[5] <= altdpram0:inst.q[5]
DATA_IO[6] <= altdpram0:inst.q[6]
DATA_IO[7] <= altdpram0:inst.q[7]


|Inter|perictr:inst1
PB_RS => FLASH_RS.DATAIN
A0 => FPS_A0.DATAIN
A15 => FLASH_A15.DATAIN
A16 => FLASH_A16.DATAIN
A17 => FLASH_A17.DATAIN
A18 => CSRAM~0.IN0
A18 => CSROM~1.IN0
A19 => CSROM~0.IN0
A20 => CSROM~0.IN1
DSP_RW => FLASH_RD~0.IN0
DSP_RW => FPS_RD~0.IN0
DSP_RW => FPS_WR.DATAIN
DSP_RW => FLASH_WR.DATAIN
FLASH_RY => DSP_READY~0.IN0
FPS_WAIT => DSP_READY~0.IN1
FPS_INTR => ~NO_FANOUT~
XF => ~NO_FANOUT~
DSP_DS => ~NO_FANOUT~
DSP_PS => ~NO_FANOUT~
DSP_IS => CS_FPS.DATAIN
DSP_MSTRB => CSRAM~1.IN0
DSP_MSTRB => CSROM~3.IN0
IOSTRB => ~NO_FANOUT~
BDX2 => ~NO_FANOUT~
CPLD_TOUT => ~NO_FANOUT~
CPLD_CLKIN => ~NO_FANOUT~
CPLD_GCLRN => ~NO_FANOUT~
CPLD_OE1 => ~NO_FANOUT~
RS <= <VCC>
INT1 <= <VCC>
INT3 <= <VCC>
NMI <= <VCC>
HOLD <= <VCC>
FLASH_A15 <= A15.DB_MAX_OUTPUT_PORT_TYPE
FLASH_A16 <= A16.DB_MAX_OUTPUT_PORT_TYPE
FLASH_A17 <= A17.DB_MAX_OUTPUT_PORT_TYPE
FLASH_BYTE <= <VCC>
CSROM <= CSROM~3.DB_MAX_OUTPUT_PORT_TYPE
FLASH_WR <= DSP_RW.DB_MAX_OUTPUT_PORT_TYPE
FLASH_RD <= FLASH_RD~0.DB_MAX_OUTPUT_PORT_TYPE
FLASH_RS <= PB_RS.DB_MAX_OUTPUT_PORT_TYPE
FPS_A0 <= A0.DB_MAX_OUTPUT_PORT_TYPE
CS_FPS <= DSP_IS.DB_MAX_OUTPUT_PORT_TYPE
FPS_RD <= FPS_RD~0.DB_MAX_OUTPUT_PORT_TYPE
FPS_WR <= DSP_RW.DB_MAX_OUTPUT_PORT_TYPE
FPS_EXINT <= FPS_EXINT~1.DB_MAX_OUTPUT_PORT_TYPE
CSRAM <= CSRAM~1.DB_MAX_OUTPUT_PORT_TYPE
BIO <= BIO~0.DB_MAX_OUTPUT_PORT_TYPE
DSP_READY <= DSP_READY~0.DB_MAX_OUTPUT_PORT_TYPE
BDR2 <= BDR2~0.DB_MAX_OUTPUT_PORT_TYPE
BCLKR2 <= BCLKR2~0.DB_MAX_OUTPUT_PORT_TYPE
BCLKX2 => ~NO_FANOUT~
BFSR2 <= BFSR2~0.DB_MAX_OUTPUT_PORT_TYPE
BFSX2 => ~NO_FANOUT~
HD0 <= HD0~0.DB_MAX_OUTPUT_PORT_TYPE
HD1 <= HD1~0.DB_MAX_OUTPUT_PORT_TYPE
HD2 <= HD2~0.DB_MAX_OUTPUT_PORT_TYPE
HD3 <= HD3~0.DB_MAX_OUTPUT_PORT_TYPE
HD4 <= HD4~0.DB_MAX_OUTPUT_PORT_TYPE
HD5 <= HD5~0.DB_MAX_OUTPUT_PORT_TYPE
HD6 <= HD6~0.DB_MAX_OUTPUT_PORT_TYPE
HD7 <= HD7~0.DB_MAX_OUTPUT_PORT_TYPE


|Inter|ReadKeyValBlock:inst4
Key_CLK => Recieve_Cnt[6].CLK
Key_CLK => Recieve_Cnt[5].CLK
Key_CLK => Recieve_Cnt[4].CLK
Key_CLK => Recieve_Cnt[3].CLK
Key_CLK => Recieve_Cnt[2].CLK
Key_CLK => Recieve_Cnt[1].CLK
Key_CLK => Recieve_Cnt[0].CLK
Key_CLK => Wr~reg0.CLK
Key_CLK => Wr_Addr~reg0.CLK
Key_CLK => Key_Data[7]~reg0.CLK
Key_CLK => Key_Data[6]~reg0.CLK
Key_CLK => Key_Data[5]~reg0.CLK
Key_CLK => Key_Data[4]~reg0.CLK
Key_CLK => Key_Data[3]~reg0.CLK
Key_CLK => Key_Data[2]~reg0.CLK
Key_CLK => Key_Data[1]~reg0.CLK
Key_CLK => Key_Data[0]~reg0.CLK
Key_CLK => falling_edge~0.IN0
Key_CLK => Recieve_Cnt[7].CLK
Key => Rx_CNT~0.IN0
Key => Recieve_Cnt~8.OUTPUTSELECT
Key => Recieve_Cnt~9.OUTPUTSELECT
Key => Recieve_Cnt~10.OUTPUTSELECT
Key => Recieve_Cnt~11.OUTPUTSELECT
Key => Recieve_Cnt~12.OUTPUTSELECT
Key => Recieve_Cnt~13.OUTPUTSELECT
Key => Recieve_Cnt~14.OUTPUTSELECT
Key => Recieve_Cnt~15.OUTPUTSELECT
iKey_SDAT => INPUT_Register~7.DATAB
Read_En => Rx_CNT~1.IN0
Read_En => Recieve_Key_Value~0.IN0
Key_Data[0] <= Key_Data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[1] <= Key_Data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[2] <= Key_Data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[3] <= Key_Data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[4] <= Key_Data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[5] <= Key_Data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[6] <= Key_Data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_Data[7] <= Key_Data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Wr_Addr <= Wr_Addr~reg0.DB_MAX_OUTPUT_PORT_TYPE
Wr <= Wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
DSP_Write_INT <= DSP_Write_INT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Inter|Send_CMD_7279A:inst3
Key_CLK => Key_CS_Delay[1].CLK
Key_CLK => Key_CS_Delay[0].CLK
Key_CLK => CLKOUT.DATAB
Key_CLK => Key_CLKOUT~0.DATAB
Key_CLK => Key_CS_Delay[2].CLK
Key_CLK => shizhong.DATAIN
Key_RESET => Key_CS_Bak.IN0
Key_RESET => Create_KeyCLK~4.IN0
Key_RESET => Create_KeyCLK~11.IN0
Key => Key_CS_Bak.IN1
Key => Create_KeyCLK~3.IN0
Key => Create_KeyCLK~11.IN1
Key => Key_CS_Delay[1].ACLR
Key => Key_CS_Delay[0].ACLR
Key => Transmit_Cnt[4].ACLR
Key => Transmit_Cnt[3].ACLR
Key => Transmit_Cnt[2].ACLR
Key => Transmit_Cnt[1].ACLR
Key => Transmit_Cnt[0].ACLR
Key => Key_CS_Delay[2].ACLR
oKey_SDAT <= Send_ReadCMDTO7279A~6.DB_MAX_OUTPUT_PORT_TYPE
Read_En <= Read_En~reg0.DB_MAX_OUTPUT_PORT_TYPE
Key_CLKOUT <= Key_CLKOUT~0.DB_MAX_OUTPUT_PORT_TYPE
Key_CS <= Create_KeyCLK~11.DB_MAX_OUTPUT_PORT_TYPE
shizhong <= Key_CLK.DB_MAX_OUTPUT_PORT_TYPE


|Inter|CLK_DIV:inst6
CPLD_CLKIN => \Make_CLK:CNT1[8].CLK
CPLD_CLKIN => \Make_CLK:CNT1[7].CLK
CPLD_CLKIN => \Make_CLK:CNT1[6].CLK
CPLD_CLKIN => \Make_CLK:CNT1[5].CLK
CPLD_CLKIN => \Make_CLK:CNT1[4].CLK
CPLD_CLKIN => \Make_CLK:CNT1[3].CLK
CPLD_CLKIN => \Make_CLK:CNT1[2].CLK
CPLD_CLKIN => \Make_CLK:CNT1[1].CLK
CPLD_CLKIN => \Make_CLK:CNT1[0].CLK
CPLD_CLKIN => CLK.CLK
PB_RS => Make_CLK~0.IN0
Key_CLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE