📄 inter.tan.qmsg

📁 cpld
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CPLD_CLKIN register Send_CMD_7279A:inst3\|Read_En register ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\] 24.15 MHz 41.4 ns Internal " "Info: Clock \"CPLD_CLKIN\" has Internal fmax of 24.15 MHz between source register \"Send_CMD_7279A:inst3\|Read_En\" and destination register \"ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\]\" (period= 41.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Send_CMD_7279A:inst3\|Read_En 1 REG LC21 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 41; REG Node = 'Send_CMD_7279A:inst3\|Read_En'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 5.900 ns ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\] 2 REG LC60 37 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 5.900 ns; Loc. = LC60; Fanout = 37; REG Node = 'ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.900 ns" { Send_CMD_7279A:inst3|Read_En ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 52.54 % " "Info: Total cell delay = 3.100 ns ( 52.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 47.46 % " "Info: Total interconnect delay = 2.800 ns ( 47.46 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.900 ns" { Send_CMD_7279A:inst3|Read_En ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { Send_CMD_7279A:inst3|Read_En ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.300 ns - Smallest " "Info: - Smallest clock skew is -10.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN destination 10.100 ns + Shortest register " "Info: + Shortest clock path from clock \"CPLD_CLKIN\" to destination register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\] 3 REG LC60 37 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC60; Fanout = 37; REG Node = 'ReadKeyValBlock:inst4\|lpm_counter:Recieve_Cnt_rtl_1\|dffs\[6\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.100 ns" { CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 71.29 % " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 28.71 % " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN source 20.400 ns - Longest register " "Info: - Longest clock path from clock \"CPLD_CLKIN\" to source register is 20.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 11.700 ns Send_CMD_7279A:inst3\|Key_CS_Delay\[1\] 3 REG LC23 13 " "Info: 3: + IC(2.900 ns) + CELL(3.800 ns) = 11.700 ns; Loc. = LC23; Fanout = 13; REG Node = 'Send_CMD_7279A:inst3\|Key_CS_Delay\[1\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.700 ns" { CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 18.200 ns Send_CMD_7279A:inst3\|CLKOUT~36 4 COMB SEXP19 2 " "Info: 4: + IC(2.700 ns) + CELL(3.800 ns) = 18.200 ns; Loc. = SEXP19; Fanout = 2; COMB Node = 'Send_CMD_7279A:inst3\|CLKOUT~36'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.500 ns" { Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 20.400 ns Send_CMD_7279A:inst3\|Read_En 5 REG LC21 41 " "Info: 5: + IC(0.000 ns) + CELL(2.200 ns) = 20.400 ns; Loc. = LC21; Fanout = 41; REG Node = 'Send_CMD_7279A:inst3\|Read_En'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.200 ns" { Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 72.55 % " "Info: Total cell delay = 14.800 ns ( 72.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 27.45 % " "Info: Total interconnect delay = 5.600 ns ( 27.45 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.000ns 0.000ns 0.000ns 2.900ns 2.700ns 0.000ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 2.200ns } } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.000ns 0.000ns 0.000ns 2.900ns 2.700ns 0.000ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.900 ns" { Send_CMD_7279A:inst3|Read_En ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { Send_CMD_7279A:inst3|Read_En ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } { 0.000ns 2.800ns } { 0.000ns 3.100ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.000ns 0.000ns 0.000ns 2.900ns 2.700ns 0.000ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 2.200ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CPLD_CLKIN 39 " "Warning: Circuit may not operate. Detected 39 non-operational path(s) clocked by clock \"CPLD_CLKIN\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\] Send_CMD_7279A:inst3\|Read_En CPLD_CLKIN 4.2 ns " "Info: Found hold time violation between source  pin or register \"Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\]\" and destination pin or register \"Send_CMD_7279A:inst3\|Read_En\" for clock \"CPLD_CLKIN\" (Hold time is 4.2 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.300 ns + Largest " "Info: + Largest clock skew is 10.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN destination 20.400 ns + Longest register " "Info: + Longest clock path from clock \"CPLD_CLKIN\" to destination register is 20.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 11.700 ns Send_CMD_7279A:inst3\|Key_CS_Delay\[1\] 3 REG LC23 13 " "Info: 3: + IC(2.900 ns) + CELL(3.800 ns) = 11.700 ns; Loc. = LC23; Fanout = 13; REG Node = 'Send_CMD_7279A:inst3\|Key_CS_Delay\[1\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.700 ns" { CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 18.200 ns Send_CMD_7279A:inst3\|CLKOUT~36 4 COMB SEXP19 2 " "Info: 4: + IC(2.700 ns) + CELL(3.800 ns) = 18.200 ns; Loc. = SEXP19; Fanout = 2; COMB Node = 'Send_CMD_7279A:inst3\|CLKOUT~36'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.500 ns" { Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 20.400 ns Send_CMD_7279A:inst3\|Read_En 5 REG LC21 41 " "Info: 5: + IC(0.000 ns) + CELL(2.200 ns) = 20.400 ns; Loc. = LC21; Fanout = 41; REG Node = 'Send_CMD_7279A:inst3\|Read_En'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.200 ns" { Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 72.55 % " "Info: Total cell delay = 14.800 ns ( 72.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 27.45 % " "Info: Total interconnect delay = 5.600 ns ( 27.45 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.0ns 0.0ns 0.0ns 2.9ns 2.7ns 0.0ns } { 0.0ns 2.5ns 2.5ns 3.8ns 3.8ns 2.2ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN source 10.100 ns - Shortest register " "Info: - Shortest clock path from clock \"CPLD_CLKIN\" to source register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\] 3 REG LC28 15 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC28; Fanout = 15; REG Node = 'Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.100 ns" { CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 71.29 % " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 28.71 % " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } { 0.0ns 0.0ns 0.0ns 2.9ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.0ns 0.0ns 0.0ns 2.9ns 2.7ns 0.0ns } { 0.0ns 2.5ns 2.5ns 3.8ns 3.8ns 2.2ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } { 0.0ns 0.0ns 0.0ns 2.9ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns - Shortest register register " "Info: - Shortest register to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\] 1 REG LC28 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC28; Fanout = 15; REG Node = 'Send_CMD_7279A:inst3\|lpm_counter:Transmit_Cnt_rtl_0\|dffs\[3\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 5.800 ns Send_CMD_7279A:inst3\|Read_En 2 REG LC21 41 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC21; Fanout = 41; REG Node = 'Send_CMD_7279A:inst3\|Read_En'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.800 ns" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 53.45 % " "Info: Total cell delay = 3.100 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 46.55 % " "Info: Total interconnect delay = 2.700 ns ( 46.55 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.800 ns" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] Send_CMD_7279A:inst3|Read_En } { 0.0ns 2.7ns } { 0.0ns 3.1ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 50 -1 0 } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Read_En } { 0.0ns 0.0ns 0.0ns 2.9ns 2.7ns 0.0ns } { 0.0ns 2.5ns 2.5ns 3.8ns 3.8ns 2.2ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] } { 0.0ns 0.0ns 0.0ns 2.9ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.800 ns" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] Send_CMD_7279A:inst3|Read_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[3] Send_CMD_7279A:inst3|Read_En } { 0.0ns 2.7ns } { 0.0ns 3.1ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "Send_CMD_7279A:inst3\|Key_CS_Delay\[0\] Key_RESET CPLD_CLKIN 0.900 ns register " "Info: tsu for register \"Send_CMD_7279A:inst3\|Key_CS_Delay\[0\]\" (data pin = \"Key_RESET\", clock pin = \"CPLD_CLKIN\") is 0.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns + Longest pin register " "Info: + Longest pin to register delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns Key_RESET 1 PIN PIN_72 5 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_72; Fanout = 5; PIN Node = 'Key_RESET'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { Key_RESET } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -352 8 176 -336 "Key_RESET" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 5.400 ns Send_CMD_7279A:inst3\|add~146 2 COMB LC25 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 5.400 ns; Loc. = LC25; Fanout = 1; COMB Node = 'Send_CMD_7279A:inst3\|add~146'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "4.000 ns" { Key_RESET Send_CMD_7279A:inst3|add~146 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 8.100 ns Send_CMD_7279A:inst3\|Key_CS_Delay\[0\] 3 REG LC26 13 " "Info: 3: + IC(0.000 ns) + CELL(2.700 ns) = 8.100 ns; Loc. = LC26; Fanout = 13; REG Node = 'Send_CMD_7279A:inst3\|Key_CS_Delay\[0\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.700 ns" { Send_CMD_7279A:inst3|add~146 Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns 66.67 % " "Info: Total cell delay = 5.400 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 33.33 % " "Info: Total interconnect delay = 2.700 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "8.100 ns" { Key_RESET Send_CMD_7279A:inst3|add~146 Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { Key_RESET Key_RESET~out Send_CMD_7279A:inst3|add~146 Send_CMD_7279A:inst3|Key_CS_Delay[0] } { 0.000ns 0.000ns 2.700ns 0.000ns } { 0.000ns 1.400ns 1.300ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN destination 10.100 ns - Shortest register " "Info: - Shortest clock path from clock \"CPLD_CLKIN\" to destination register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 10.100 ns Send_CMD_7279A:inst3\|Key_CS_Delay\[0\] 3 REG LC26 13 " "Info: 3: + IC(2.900 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC26; Fanout = 13; REG Node = 'Send_CMD_7279A:inst3\|Key_CS_Delay\[0\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "5.100 ns" { CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 71.29 % " "Info: Total cell delay = 7.200 ns ( 71.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 28.71 % " "Info: Total interconnect delay = 2.900 ns ( 28.71 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "8.100 ns" { Key_RESET Send_CMD_7279A:inst3|add~146 Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { Key_RESET Key_RESET~out Send_CMD_7279A:inst3|add~146 Send_CMD_7279A:inst3|Key_CS_Delay[0] } { 0.000ns 0.000ns 2.700ns 0.000ns } { 0.000ns 1.400ns 1.300ns 2.700ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "10.100 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[0] } { 0.000ns 0.000ns 0.000ns 2.900ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CPLD_CLKIN Key_SDAT Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1 29.600 ns register " "Info: tco from clock \"CPLD_CLKIN\" to destination pin \"Key_SDAT\" through register \"Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1\" is 29.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CPLD_CLKIN source 20.400 ns + Longest register " "Info: + Longest clock path from clock \"CPLD_CLKIN\" to source register is 20.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CPLD_CLKIN 1 CLK PIN_90 10 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_90; Fanout = 10; CLK Node = 'CPLD_CLKIN'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { CPLD_CLKIN } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { -336 8 176 -320 "CPLD_CLKIN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns CLK_DIV:inst6\|Key_CLK 2 REG LC1 43 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC1; Fanout = 43; REG Node = 'CLK_DIV:inst6\|Key_CLK'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.500 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK } "NODE_NAME" } "" } } { "CLK_DIV.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/CLK_DIV.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 11.700 ns Send_CMD_7279A:inst3\|Key_CS_Delay\[1\] 3 REG LC23 13 " "Info: 3: + IC(2.900 ns) + CELL(3.800 ns) = 11.700 ns; Loc. = LC23; Fanout = 13; REG Node = 'Send_CMD_7279A:inst3\|Key_CS_Delay\[1\]'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.700 ns" { CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 98 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 18.200 ns Send_CMD_7279A:inst3\|CLKOUT~36 4 COMB SEXP19 2 " "Info: 4: + IC(2.700 ns) + CELL(3.800 ns) = 18.200 ns; Loc. = SEXP19; Fanout = 2; COMB Node = 'Send_CMD_7279A:inst3\|CLKOUT~36'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "6.500 ns" { Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 } "NODE_NAME" } "" } } { "Send_CMD_7279A.vhd" "" { Text "E:/otherpersondata/hk/Inter（629）/Send_CMD_7279A.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 20.400 ns Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1 5 REG LC24 1 " "Info: 5: + IC(0.000 ns) + CELL(2.200 ns) = 20.400 ns; Loc. = LC24; Fanout = 1; REG Node = 'Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "2.200 ns" { Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 72.55 % " "Info: Total cell delay = 14.800 ns ( 72.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 27.45 % " "Info: Total interconnect delay = 5.600 ns ( 27.45 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } { 0.000ns 0.000ns 0.000ns 2.900ns 2.700ns 0.000ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register pin " "Info: + Longest register to pin delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1 1 REG LC24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC24; Fanout = 1; REG Node = 'Send_CMD_7279A:inst3\|Send_ReadCMDTO7279A~1'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(5.000 ns) 7.600 ns Key_SDAT 2 PIN PIN_79 0 " "Info: 2: + IC(2.600 ns) + CELL(5.000 ns) = 7.600 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'Key_SDAT'" {  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "7.600 ns" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 Key_SDAT } "NODE_NAME" } "" } } { "inter.bdf" "" { Schematic "E:/otherpersondata/hk/Inter（629）/inter.bdf" { { 152 760 936 168 "Key_SDAT" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 65.79 % " "Info: Total cell delay = 5.000 ns ( 65.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 34.21 % " "Info: Total interconnect delay = 2.600 ns ( 34.21 % )" {  } {  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "7.600 ns" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 Key_SDAT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.600 ns" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 Key_SDAT } { 0.000ns 2.600ns } { 0.000ns 5.000ns } } }  } 0}  } { { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "20.400 ns" { CPLD_CLKIN CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.400 ns" { CPLD_CLKIN CPLD_CLKIN~out CLK_DIV:inst6|Key_CLK Send_CMD_7279A:inst3|Key_CS_Delay[1] Send_CMD_7279A:inst3|CLKOUT~36 Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 } { 0.000ns 0.000ns 0.000ns 2.900ns 2.700ns 0.000ns } { 0.000ns 2.500ns 2.500ns 3.800ns 3.800ns 2.200ns } } } { "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" "" { Report "E:/otherpersondata/hk/Inter（629）/db/Inter_cmp.qrpt" Compiler "Inter" "UNKNOWN" "V1" "E:/otherpersondata/hk/Inter（629）/db/Inter.quartus_db" { Floorplan "E:/otherpersondata/hk/Inter（629）/" "" "7.600 ns" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 Key_SDAT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.600 ns" { Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1 Key_SDAT } { 0.000ns 2.600ns } { 0.000ns 5.000ns } } }  } 0}
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