lcd_display.vhd

cpld

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
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-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Sun May 15 20:36:32 2005

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY LCD_Display IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CPLD_CLKIN : IN STD_LOGIC;
		DSP_MSTRB : IN STD_LOGIC;
		DSP_RW : IN STD_LOGIC;
		A18 : IN STD_LOGIC;
		A19 : IN STD_LOGIC;
		A20 : IN STD_LOGIC;
		LCD_RS : OUT STD_LOGIC;
		LCD_RW : OUT STD_LOGIC;
		LCD_E : OUT STD_LOGIC;
		LCD_CS1 : OUT STD_LOGIC;
		LCD_CS2 : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END LCD_Display;


--  Architecture Body

ARCHITECTURE LCD_Display_architecture OF LCD_Display IS

	
SIGNAL  Addr_Code : STD_LOGIC_VECTOR(1 DOWNTO 0) ;

BEGIN
         --在A20＝1时对LCD访问。
        LCD_RW<=DSP_RW WHEN  A20='1' ELSE 'Z';
--------------------------------------------------------------

Get_Address:
 PROCESS(A20,A19,A18)
 
   BEGIN   
   
        IF A20='1' THEN
    
            Addr_Code<=A19 & A18;

        ELSE
            Addr_Code<="ZZ";

       END IF;

END PROCESS  Get_Address;
----------------------------------------------------------------

Address_Coding:
 PROCESS(Addr_Code)
  
    BEGIN
              
         CASE Addr_Code IS
           
             WHEN "00" => LCD_CS1<='0';  --Write COM to Left Chip
                          LCD_CS2<='1';
                          LCD_RS<='0';
             
             WHEN "01" => LCD_CS1<='0';  --Write DATA to Left Chip
                          LCD_CS2<='1';
                          LCD_RS<='1';
             
             WHEN "10" => LCD_CS1<='1';  --Write COM to Right Chip
                          LCD_CS2<='0';
                          LCD_RS<='0'; 

             WHEN "11" => LCD_CS1<='1';  --Write DATA to Right Chip
                          LCD_CS2<='0';
                          LCD_RS<='1';
              
         --   WHEN OTHERS =>LCD_CS1<='Z';  
        --                  LCD_CS2<='Z';
         --                 LCD_RS<='Z';
        END CASE;   

END PROCESS Address_Coding;
--------------------------------------------------------------


Create_LCD_En :
   PROCESS(CPLD_CLKIN) 
 
     BEGIN 
            IF falling_edge(CPLD_CLKIN) THEN
                  
                 IF A20='1' AND DSP_MSTRB='0' AND DSP_RW='0' THEN
                      
                    LCD_E<='0';

                  ELSE 
                
                    LCD_E<='1';

                 END IF;

              END IF;

   END PROCESS Create_LCD_En;  
------------------------------------------------------------  

END LCD_Display_architecture;