首页 › 资源下载 › VHDL/FPGA/Verilog › cpld › 源码查看
inter.vwf

来自「cpld」· VWF 代码 · 共 2,781 行 · 第 1/4 页
VWF
2,781 行
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[0][1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[0]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[0][0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[0]";
}

SIGNAL("ReadKeyValBlock:inst4|Wr_Addr")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("Inter|altdpram0:inst|altdpram:altdpram_component|rden")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("Inter|altdpram0:inst|q")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("Inter|altdpram0:inst|q[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|q[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "Inter|altdpram0:inst|q";
}

SIGNAL("Inter|altdpram0:inst|rden")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("Inter|altdpram0:inst|altdpram:altdpram_component|rdaddress[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("Inter|altdpram0:inst|altdpram:altdpram_component|rdaddress")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("altdpram0:inst|altdpram:altdpram_component|cells[1][0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "altdpram0:inst|altdpram:altdpram_component|cells[1]";
}

SIGNAL("Inter|altdpram0:inst|altdpram:altdpram_component|wren")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("Inter|CLK_DIV:inst6|CLK_Delay")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = COMBINATORIAL;
	PARENT = "";
}

SIGNAL("HD6")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("HD7")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("DSP_RW")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 418150.0;
		LEVEL 0 FOR 141005.0;
		LEVEL 1 FOR 2440845.0;
	}
}

TRANSITION_LIST("Key")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 18750.0;
		LEVEL 0 FOR 981250.0;
		LEVEL 1 FOR 18750.0;
		LEVEL 0 FOR 981250.0;
		NODE
		{
			REPEAT = 1;
			LEVEL 1 FOR 18750.0;
			LEVEL 0 FOR 981250.0;
		}
	}
}

TRANSITION_LIST("Key_SDAT")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 246630.0;
		LEVEL 1 FOR 70755.0;
		LEVEL 0 FOR 57615.0;
		LEVEL 1 FOR 98685.0;
		LEVEL 0 FOR 54920.0;
		LEVEL 1 FOR 140730.0;
		LEVEL Z FOR 87600.0;
		LEVEL 1 FOR 154560.0;
		LEVEL Z FOR 296080.0;
		LEVEL 1 FOR 15930.0;
		LEVEL 0 FOR 20535.0;
		LEVEL 1 FOR 115005.0;
		LEVEL 0 FOR 136890.0;
		LEVEL Z FOR 55255.0;
		LEVEL 1 FOR 178125.0;
		LEVEL Z FOR 478260.0;
		LEVEL 1 FOR 15930.0;
		LEVEL 0 FOR 20535.0;
		LEVEL 1 FOR 115005.0;
		LEVEL 0 FOR 136890.0;
		LEVEL Z FOR 55255.0;
		LEVEL 1 FOR 178125.0;
		LEVEL Z FOR 270685.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|INPUT_Register[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DATA_IO[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("DSP_MSTRB")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("ReadKeyValBlock:inst4|Recieve_Cnt[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("PB_RS")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 3000000.0;
	}
}

TRANSITION_LIST("Key_CS")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 3000000.0;
	}
}

TRANSITION_LIST("Key_RESET")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 3000000.0;
	}
}

TRANSITION_LIST("DSP_Write_INT2")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 3000000.0;
	}
}

TRANSITION_LIST("CPLD_CLKIN")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 60000;
			LEVEL 0 FOR 25.0;
			LEVEL 1 FOR 25.0;
		}
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
	}
}

TRANSITION_LIST("Send_CMD_7279A:inst3|Transmit_Cnt[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 3000000.0;
inter.vwf - 源码说明

本页面展示了「cpld」中的 inter.vwf 源码文件，采用 VWF 编程语言编写，共 2,781 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
虫虫开发者社区收录了大量与CPLD相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。
⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?