inter_pt_vhd.tcl

cpld

## Copyright (C) 1991-2004 Altera Corporation
## Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
## support information,  device programming or simulation file,  and any other
## associated  documentation or information  provided by  Altera  or a partner
## under  Altera's   Megafunction   Partnership   Program  may  be  used  only
## to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
## other  use  of such  megafunction  design,  netlist,  support  information,
## device programming or simulation file,  or any other  related documentation
## or information  is prohibited  for  any  other purpose,  including, but not
## limited to  modification,  reverse engineering,  de-compiling, or use  with
## any other  silicon devices,  unless such use is  explicitly  licensed under
## a separate agreement with  Altera  or a megafunction partner.  Title to the
## intellectual property,  including patents,  copyrights,  trademarks,  trade
## secrets,  or maskworks,  embodied in any such megafunction design, netlist,
## support  information,  device programming or simulation file,  or any other
## related documentation or information provided by  Altera  or a megafunction
## partner, remains with Altera, the megafunction partner, or their respective
## licensors. No other licenses, including any licenses needed under any third
## party's intellectual property, are provided herein.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 4.2 Build 156 11/29/2004 SJ Web Edition"

## DATE "05/09/2006 22:33:57"

## 
## Device: Altera EPM3128ATC100-10 Package TQFP100
## 

## 
## This Tcl script should be used for PrimeTime (VHDL) only
## 

## This file can be sourced in primetime

set timing_propagate_single_condition_min_slew false
set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "d:/altera/quartus42/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  max_asynch_io_lib.db max_mcell_register_lib.db  max_asynch_mcell_lib.db max_asynch_sexp_lib.db  alt_vtl.db]

read_vhdl  -vhdl_compiler  max_all_pt.vhd 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_vhdl  -vhdl_compiler Inter.vho
current_design Inter
link
read_sdf Inter_vhd.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
# WARNING : The required clock period is not set.The default value (100 ns) is used.
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports CPLD_CLKIN ] -name CPLD_CLKIN  

set_propagated_clock [all_clocks]
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
set grp_prj_wide_tsu_inputs [get_ports {A15 A16 A17 A18 DSP_MSTRB A20 A19 DSP_RW PB_RS A0 DSP_IS FLASH_RY FPS_WAIT Key_RESET Key Key_SDAT DATA_IO[7] DATA_IO[6] DATA_IO[5] DATA_IO[4] \
    DATA_IO[3] DATA_IO[2] DATA_IO[1] DATA_IO[0]} ]
set grp_prj_wide_tco_outputs [get_ports {RS INT1 INT3 NMI HOLD FLASH_A15 FLASH_A16 FLASH_A17 FLASH_BYTE CSROM FLASH_WR FLASH_RD FLASH_RS FPS_A0 CS_FPS FPS_RD FPS_WR FPS_EXINT CSRAM BIO \
    DSP_READY BDR2 DSP_Write_INT2 Key_CS LCD_RS LCD_RW LCD_E LCD_CS1 LCD_CS2 BCLKR2 BFSR2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 Key_CLKOUT Key_SDAT DATA_IO[7] DATA_IO[6] DATA_IO[5] \
    DATA_IO[4] DATA_IO[3] DATA_IO[2] DATA_IO[1] DATA_IO[0]} ]
set grp_prj_wide_th_inputs [get_ports {A15 A16 A17 A18 DSP_MSTRB A20 A19 DSP_RW PB_RS A0 DSP_IS FLASH_RY FPS_WAIT Key_RESET Key Key_SDAT DATA_IO[7] DATA_IO[6] DATA_IO[5] DATA_IO[4] \
    DATA_IO[3] DATA_IO[2] DATA_IO[1] DATA_IO[0]} ]
set grp_prj_wide_min_tco_outputs [get_ports {RS INT1 INT3 NMI HOLD FLASH_A15 FLASH_A16 FLASH_A17 FLASH_BYTE CSROM FLASH_WR FLASH_RD FLASH_RS FPS_A0 CS_FPS FPS_RD FPS_WR FPS_EXINT CSRAM BIO \
    DSP_READY BDR2 DSP_Write_INT2 Key_CS LCD_RS LCD_RW LCD_E LCD_CS1 LCD_CS2 BCLKR2 BFSR2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 Key_CLKOUT Key_SDAT DATA_IO[7] DATA_IO[6] DATA_IO[5] \
    DATA_IO[4] DATA_IO[3] DATA_IO[2] DATA_IO[1] DATA_IO[0]} ]

foreach_in_collection clk_item [all_clocks] {
  # Input delay for setup time.
	set_input_delay -max -add_delay 0.00 -clock [get_clocks $clk_item] $grp_prj_wide_tsu_inputs
  # Input delay for hold time.
	set_input_delay -min -add_delay 0.00 -clock [get_clocks $clk_item] $grp_prj_wide_th_inputs
  # Max output delay for clock-to-output.
	set_output_delay -max -add_delay 0.00 -clock [get_clocks $clk_item] $grp_prj_wide_tco_outputs
  # Min output delay for clock-to-output.
	set_output_delay -min -add_delay 0.00 -clock [get_clocks $clk_item] $grp_prj_wide_min_tco_outputs
}
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
# Warning: using default load capacitance for LVTTL output port
set_load 10 [get_ports { RS INT1 INT3 NMI HOLD FLASH_A15 FLASH_A16 FLASH_A17 FLASH_BYTE CSROM FLASH_WR FLASH_RD FLASH_RS FPS_A0 CS_FPS FPS_RD FPS_WR FPS_EXINT CSRAM BIO DSP_READY \
    BDR2 DSP_Write_INT2 Key_CS LCD_RS LCD_RW LCD_E LCD_CS1 LCD_CS2 BCLKR2 BFSR2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 Key_CLKOUT Key_SDAT DATA_IO[7] DATA_IO[6] DATA_IO[5] DATA_IO[4] \
    DATA_IO[3] DATA_IO[2] DATA_IO[1] DATA_IO[0] } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##
unset grp_prj_wide_tsu_inputs
unset grp_prj_wide_tco_outputs
unset grp_prj_wide_th_inputs
unset grp_prj_wide_min_tco_outputs

update_timing