📄 send_cmd_7279a.vhd
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Thu May 05 16:53:16 2005
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.TYPES.ALL;
USE WORK.FUNCTIONS.ALL;
-- Entity Declaration
ENTITY Send_CMD_7279A IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
Key_CLK : IN STD_LOGIC;
Key_RESET : IN STD_LOGIC;
Key : IN STD_LOGIC;
oKey_SDAT : OUT STD_LOGIC;
Read_En : OUT STD_LOGIC;
Key_CLKOUT :OUT STD_LOGIC;
Key_CS : OUT STD_LOGIC;
shizhong:out std_logic
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END Send_CMD_7279A;
-- Architecture Body
ARCHITECTURE Send_CMD_7279A_architecture OF Send_CMD_7279A IS
--CtrCMD Define:
CONSTANT RESET_CMD :STD_LOGIC_VECTOR(7 DOWNTO 0):="10100100";
CONSTANT READ_KeyBoard_CMD :STD_LOGIC_VECTOR(7 DOWNTO 0):="00010101";
CONSTANT TEST_CMD :STD_LOGIC_VECTOR(7 DOWNTO 0):="10111111";
--Register Define:
SIGNAL Transmit_Cnt:INTEGER RANGE 0 TO 20;
-- SIGNAL Transmit_Cnt_Stop :STD_LOGIC;
SIGNAL Transmit_Cnt1:INTEGER RANGE 0 TO 20;
SIGNAL OUTPUT_Register:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Reset_Over:STD_LOGIC;
SIGNAL CLKOUT:STD_LOGIC;
SIGNAL Key_CS_Delay:INTEGER RANGE 0 TO 4;
SIGNAL Key_CS_Bak:STD_LOGIC;
SIGNAL Key_CS_Delay_Stop: STD_LOGIC;--CS有效后,延时发送读命令
CONSTANT Stop_Length:INTEGER:=3;--Key_Cs到启动时钟的时间间隔
CONSTANT Tx_STOP_BIT:INTEGER:=9;
CONSTANT Rx_START_BIT:INTEGER:=12;
CONSTANT Rx_STOP_BIT:INTEGER:=20;
CONSTANT Tx_CNT_STOP_BIT:INTEGER:=30;
BEGIN
Key_CS<= Key AND Key_RESET;
Key_CS_Bak<=Key AND Key_RESET;
Create_KeyCLK:
PROCESS(Key,Key_CLK,Key_CS_Delay,Key_RESET,Transmit_Cnt)
BEGIN
IF rising_edge(Key_CLK) THEN
IF Key_CS_Bak='0' AND Key_CS_Delay_Stop ='0' THEN
Key_CS_Delay<=Key_CS_Delay+1;
END IF;
END IF;
------------------
IF Key_CS_Delay>= Stop_Length THEN --时间延迟长度
CLKOUT<=Key_CLK;
Key_CS_Delay_Stop<='1'; --停止计数
ELSE
Key_CS_Delay_Stop<='0';
CLKOUT<='0';
END IF;
--------------------------------------
--========================================================================
--产生键盘读写时钟
IF (Key_CS_Delay>=Stop_Length )
AND (Key='0' OR Key_RESET='0')
AND ((Transmit_Cnt>0 AND Transmit_Cnt<=Tx_STOP_BIT) OR (Transmit_Cnt> Rx_START_BIT AND Transmit_Cnt<=Rx_STOP_BIT)) THEN
Key_CLKOUT<=Key_CLK;
ELSIF (Key='1' AND Key_RESET='1')
OR Key_CS_Delay < Stop_Length THEN
Key_CLKOUT<='1';
ELSE
Key_CLKOUT<='0';
END IF;
--====================================================================
IF Key='1' THEN
Key_CS_Delay<=0;
END IF;
END PROCESS Create_KeyCLK;
--===================================================================
Tx_CNT:PROCESS(CLKOUT,Key)
BEGIN
IF rising_edge(CLKOUT) THEN
IF Transmit_Cnt<=Tx_CNT_STOP_BIT THEN
Transmit_Cnt<=Transmit_Cnt+1;
END IF;
END IF;
IF Key='1' THEN
Transmit_Cnt<=0;
END IF;
END PROCESS Tx_CNT;
----------------------------
--发送读键盘命令
Send_ReadCMDTO7279A:PROCESS( CLKOUT)
BEGIN
-- IF falling_edge(CLKOUT) THEN --时钟下沿送数据到Key_SDAT,在上升沿写入7279A
-----------------------------------------------------------------
-- IF Key_RESET = '0' THEN
-- Transmit_Cnt1<=Transmit_Cnt1+1;
-- IF Transmit_Cnt1<8 AND Reset_Over='0' THEN
-- oKey_SDAT<=PST(RESET_CMD,Transmit_Cnt1);
-- END IF;
-- IF Transmit_Cnt1>=8 THEN
-- Reset_Over<='1';
-- oKey_SDAT<='Z';
-- END IF;
-- IF Reset_Over='1' THEN
-- Transmit_Cnt1<=0;
-- END IF;
-- IF Key_RESET = '1' THEN
--
-- Reset_Over<='0' ;
-- END IF;
-- END IF;
-----------------------------------------------
-- IF Key='0' THEN -- AND Transmit_Cnt_Stop='0'
-- Transmit_Cnt<=Transmit_Cnt+1;
IF falling_edge(CLKOUT) THEN
IF Transmit_Cnt<=Tx_STOP_BIT-1 THEN
oKey_SDAT<=PST(READ_KeyBoard_CMD,Transmit_Cnt-1);
--oKey_SDAT<=PST(TEST_CMD,Transmit_Cnt-1);
END IF;
IF Transmit_Cnt>=Tx_STOP_BIT THEN
oKey_SDAT<='Z';
END IF ;
IF Transmit_Cnt>=Rx_START_BIT AND Transmit_Cnt<=Rx_STOP_BIT+2 THEN
Read_En<='1';
ELSE
Read_En<='0';
END IF;
END IF;
END PROCESS Send_ReadCMDTO7279A;
shizhong<=Key_CLK;
END Send_CMD_7279A_architecture;
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