ram.vhd

cpld

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-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Mon May 09 16:41:31 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


--  Entity Declaration

ENTITY RAM IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CPLD_CLKIN : IN STD_LOGIC;
		DSP_RW : IN STD_LOGIC;
		DSP_MSTRB : IN STD_LOGIC;
		A19 : IN STD_LOGIC;
		A0:  IN STD_LOGIC;
		Read_Done : IN STD_LOGIC;
		DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
		DSP_Write_Flag : OUT STD_LOGIC;
		DSP_Write_INT : OUT STD_LOGIC;
		DATA_IO : INOUT STD_LOGIC_VECTOR(7 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END RAM;


--  Architecture Body

ARCHITECTURE RAM_architecture OF RAM IS

	

SUBTYPE BYTE    IS STD_LOGIC_VECTOR(7 DOWNTO 0) ;
TYPE    MEMORY  IS ARRAY (0 TO 1)  OF BYTE;

SIGNAL ADR_IN:  INTEGER RANGE 0 TO 7;

SIGNAL SRAM:   MEMORY;   
         
--Note: SRAM(0)<-> instruction Memory  A19='1'  A2A1A0="000" 
--      SRAM(1)<-> Data Memory         A19='1'  A2A1A0="001

--读写旗标信号
SIGNAL DSP_Read_Done:STD_LOGIC;  --DSP读出
SIGNAL DSP_Write_Done:STD_LOGIC; --DSP写入标志

BEGIN  
---------------------------------------------------

         ADR_IN <= CONV_INTEGER( (NOT A19) & A0);

-----------------------------------------------

----------------------------------------------- 

Write_KeyValue_SRAM:
PROCESS(CPLD_CLKIN) 

BEGIN 

    IF falling_edge(CPLD_CLKIN) THEN
     -----------------------------------------------------
     ---DSP 向CPLD 写数据 SRAM(0)

         IF DSP_RW='0' AND A19='1' AND DSP_MSTRB='0' THEN
                    
                SRAM(ADR_IN)<=DATA_IO;--通过地址线寻址
              
                 DSP_Write_Flag<='1'; 

              ELSE 
              
                DSP_Write_Flag<='0';
              
              END IF ;
   
   
     ----------------------------------------------------
       --写键值      SRAM(1)
      IF DSP_Read_Done='1' THEN

             SRAM(1) <="00000000";
            -- DSP_Write_INT<='1';

      END IF ; 
    
      IF    SRAM(1) ="00000000" THEN
                
              DSP_Write_INT<='1';
         
          IF  Read_Done='1' THEN

             SRAM(1)<=DATA_IN;
             DSP_Write_INT<='0'; 
         
          END IF;
     
     END IF ;

END IF;

END PROCESS Write_KeyValue_SRAM;
---------------------------------------------------

---------------------------------------------------       
DSP_Read:
PROCESS(CPLD_CLKIN)
 
BEGIN

IF falling_edge(CPLD_CLKIN) THEN

    IF  DSP_RW='1'  AND A19='1' AND SRAM(1)/="00000000" THEN  --地址有效时送数据
         
          DATA_IO<=SRAM(ADR_IN);   --数据送总线。
          DSP_Read_Done<='1' ; 
        
    END IF; 
     
    IF  SRAM(1)="00000000" THEN 

          DATA_IO<="ZZZZZZZZ";
          DSP_Read_Done<='0';  

    END IF ;

END IF;

 END PROCESS DSP_Read;
---------------------------------------------

END RAM_architecture;