read_keyval.vhd

cpld

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Thu May 05 16:52:08 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.TYPES.ALL;
USE WORK.FUNCTIONS.ALL;

--  Entity Declaration

ENTITY Read_KeyVal IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		Key_CLK : IN STD_LOGIC;
		Key : IN STD_LOGIC;
		Key_SDAT : IN STD_LOGIC;
		Read_En : IN STD_LOGIC;
		DATA : OUT STD_LOGIC_VECTOR(7 downto 0);
		Read_Done : INOUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END Read_KeyVal;


--  Architecture Body

ARCHITECTURE Read_KeyVal_architecture OF Read_KeyVal IS

SIGNAL Recieve_Cnt:INTEGER RANGE 0 TO 10;
SIGNAL INPUT_Register:BITS_8; 
	
BEGIN

Read_Key_Value: PROCESS(Key_CLK)

 BEGIN
   
     IF rising_edge(Key_CLK) THEN--时钟上降沿读数据
       
         IF Key='0' AND Read_En='1' THEN --Send_Done='1' 时接收数据
           
             Recieve_Cnt<=Recieve_Cnt+1; 
         
             INPUT_Register(0)<=Key_SDAT;    
             INPUT_Register(7 DOWNTO 1)<=INPUT_Register(6 DOWNTO 0); 
            
          END IF; 

          IF Recieve_Cnt>=8  THEN                                                                                                                                                                                                                                                                                                                                                                                           
            
             Read_Done<='1'; ---保持
          ELSE
           
             Read_Done<='0';
             
          END IF;
        
        IF Key='1' THEN
             Recieve_Cnt<=0;
        --    Read_Done<='0';

         END IF;     
   END IF;
          
 END PROCESS Read_Key_Value;

-----------------------------------------------
Send_To_Bus:PROCESS(Read_Done)

 BEGIN
    
  
         IF rising_edge(Read_Done) THEN
             DATA<=INPUT_Register;
         END IF;
 
         
END PROCESS Send_To_Bus; 
-------------


END Read_KeyVal_architecture;