inter.tan.rpt

cpld

; Worst-case tpd               ; N/A                                      ; None          ; 14.200 ns                        ; DSP_RW                                                      ; DATA_IO[7]                                                  ;            ;            ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 4.300 ns                         ; Key_SDAT                                                    ; ReadKeyValBlock:inst4|INPUT_Register[0]                     ;            ; CPLD_CLKIN ; 0            ;
; Clock Setup: 'CPLD_CLKIN'    ; N/A                                      ; None          ; 24.15 MHz ( period = 41.400 ns ) ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[3] ; CPLD_CLKIN ; CPLD_CLKIN ; 0            ;
; Clock Hold: 'CPLD_CLKIN'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|dffs[2] ; Send_CMD_7279A:inst3|Send_ReadCMDTO7279A~1                  ; CPLD_CLKIN ; CPLD_CLKIN ; 39           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                             ;                                                             ;            ;            ; 39           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM3128ATC100-10   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CPLD_CLKIN      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CPLD_CLKIN'                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                        ; To                                                          ; From Clock ; To Clock   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 24.15 MHz ( period = 41.400 ns )                    ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[6] ; CPLD_CLKIN ; CPLD_CLKIN ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 24.15 MHz ( period = 41.400 ns )                    ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[7] ; CPLD_CLKIN ; CPLD_CLKIN ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 24.15 MHz ( period = 41.400 ns )                    ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[4] ; CPLD_CLKIN ; CPLD_CLKIN ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 24.15 MHz ( period = 41.400 ns )                    ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[5] ; CPLD_CLKIN ; CPLD_CLKIN ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 24.15 MHz ( period = 41.400 ns )                    ; Send_CMD_7279A:inst3|Read_En                                ; ReadKeyValBlock:inst4|lpm_counter:Recieve_Cnt_rtl_1|dffs[0] ; CPLD_CLKIN ; CPLD_CLKIN ; None                        ; None                      ; 5.900 ns                ;